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MM74HC137 Datasheet(PDF) 1 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. MM74HC137
Description  3-to-8 Line Decoder With Address Latches (Inverted Output)
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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MM74HC137 Datasheet(HTML) 1 Page - National Semiconductor (TI)

   
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TLF5310
November 1995
MM54HC137MM74HC137 3-to-8 Line
Decoder With Address Latches
(Inverted Output)
General Description
This device utilizes advanced silicon-gate CMOS technolo-
gy to implement a three-to-eight line decoder with latches
on the three address inputs When GL goes from low to
high the address present at the select inputs (A B and C) is
stored in the latches As long as GL remains high no ad-
dress changes will be recognized Output enable controls
G1 and G2 control the state of the outputs independently of
the select or latch-enable inputs All of the outputs are high
unless G1 is high and G2 is low The HC137 is ideally suited
for the implementation of glitch-free decoders in stored-ad-
dress applications in bus oriented systems
The 54HC74HC logic family is speed function and pin-out
compatible with the standard 54LS74LS logic family All
inputs are protected from damage due to static discharge by
diodes to VCC and ground
Features
Y
Typical propagation delay 20 ns
Y
Wide supply range 2 – 6V
Y
Latched inputs for easy interfacing
Y
Fanout of 10 LS-TTL loads
Connection and Functional Block Diagrams
Dual-In-Line Package
TLF5310 – 1
Order Number MM54HC137
or MM74HC137
TLF5310 – 2
C1995 National Semiconductor Corporation
RRD-B30M115Printed in U S A


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