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IDT79R4700-200DF Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT79R4700-200DF Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 25 page 4 of 25 April 10, 2001 IDT79R4700 occurrence of an interlock or stall, a required number of processor internal cycles must occur between an integer multiply or divide and a subsequent MFHI or MFLO operation. Floating-Point Co-Processor Floating-Point Co-Processor Floating-Point Co-Processor Floating-Point Co-Processor The RC4700 incorporates a complete floating-point co-processor on chip and includes a floating-point register file and execution units. The floating-point co-processor forms a “seamless” interface with the integer unit, decoding and executing instructions in parallel with the integer unit. Floating-Point Units Floating-Point Units Floating-Point Units Floating-Point Units The RC4700 floating-point execution units support single and double precision arithmetic, as specified in the IEEE Standard 754. The execu- tion unit is separated into a multiply unit and a combined add/convert/ divide/square root unit. Overlap of multiplies and add/subtract is supported. The multiplier is partially pipelined, allowing a new multiply to begin every four cycles. The RC4700 maintains fully precise floating-point exceptions while allowing both overlapped and pipelined operations. Precise exceptions are extremely important in mission-critical environments and highly desirable for debugging in any environment. The floating-point unit operation’s set includes floating-point add, subtract, multiply, divide, square root, conversion between fixed-point and floating-point format, conversion among floating-point formats and floating-point compare. These operations comply with the IEEE Stan- dard 754. Table 1 lists the latencies of some of the floating-point instructions in internal processor cycles. Note that multiplies are pipelined so that a new multiply can be initiated every four pipeline cycles Floating-Point General Register File Floating-Point General Register File Floating-Point General Register File Floating-Point General Register File The floating-point register file is made up of thirty-two 64-bit regis- ters. With the LDC1 and SDC1 instructions the floating-point unit can take advantage of the 64-bit wide data cache and issue a co-processor load or store doubleword instruction in every cycle. The floating-point control register space contains two registers: one for determining configuration and revision information for the copro- cessor and one for control and status information. These are primarily involved with diagnostic software, exception handling, state saving and restoring, and control of rounding modes. Operation 32-bit 64-bit MULT 6 - 9 7 - 10 DIV 42 74 System Control Co-processor (CP0) System Control Co-processor (CP0) System Control Co-processor (CP0) System Control Co-processor (CP0) The system control co-processor in the MIPS architecture is respon- sible for the virtual memory sub-system, the exception control system and the diagnostics capability of the processor. In the MIPS architec- ture, the system control co-processor (and thus the kernel software) is implementation dependent. System Control Co-Processor Registers System Control Co-Processor Registers System Control Co-Processor Registers System Control Co-Processor Registers The RC4700 incorporates all system control co-processor (CP0) registers, on-chip. These registers (shown in Figure 1 on page 2) provide the path through which the virtual memory system’s page mapping is examined and changed, exceptions are handled and oper- ating modes are controlled (kernel vs. user mode, interrupts enabled or disabled, cache features). In addition, to aid in cache diagnostic testing and assist in data error detection, the RC4700 includes registers to implement a real-time cycle counting facility. Virtual-to-Physical Address Mapping Virtual-to-Physical Address Mapping Virtual-to-Physical Address Mapping Virtual-to-Physical Address Mapping To establish a secure environment for user processing, the RC4700 provides the user, supervisor, and kernel modes of virtual addressing, available to system software. Bits in a status register determine which virtual addressing mode is used. While in user mode, the RC4700 provides a single, uniform virtual address space of 256GB (2GB for 32-bit address mode). When oper- ating in the kernel mode, four distinct virtual address spaces—totalling 1024GB (4GB in 32-bit address mode)—are simultaneously available and are differentiated by the high-order bits of the virtual address. Operation Single Precision Double Precision ADD 4 4 SUB 4 4 MUL 4 5 DIV 32 61 SQRT 31 60 CMP 3 3 FIX 4 4 FLOAT 6 6 ABS 1 1 MOV 1 1 NEG 1 1 LWC1, LDC1 2 2 SWC1, SDC1 1 1 Table 1 RC4700 Instruction Latencies |
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