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IDT79RV4700-133DF Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT79RV4700-133DF Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 25 page  2 of 25 April 10, 2001 IDT79R4700 This data sheet provides an overview of the R4700’s CPU features and architecture. A more detailed description of this processor is provided in the IDT79R4700 RISC Processor Hardware User’s Manual, available from Integrated Device Technology (IDT). Information on development support, applications notes and complementary products is available on the IDT Web site www.idt.com or through your local IDT sales representative. Note: Throughout this data sheet and any other IDT materials for this device, the R4700 indicates a 5V part; RV4700 designates a reduced voltage (3V) part; and the RC4700 reflects either. Figure 1 The RC4700 CPO Registers Hardware Overview Hardware Overview Hardware Overview Hardware Overview The RC4700 processor family brings a high-level of integration designed for high-performance computing. The R4700’s key elements are briefly described below. A more detailed explanation of each subsystem is available in the user’s manual. Pipeline Pipeline Pipeline Pipeline The RC4700 uses a simple 5-stage pipeline, similar to the pipeline structure implemented in the IDT79R32364. This pipeline’s simplicity allows the RC4700 to be lower cost and lower power than super-scalar or super-pipelined processors. The pipeline stages are shown in Figure 3 on page 3. Integer Execution Engine Integer Execution Engine Integer Execution Engine Integer Execution Engine The R4700 implements the MIPS-III Instruction Set architecture and is upwardly compatible with applications that run on earlier generation parts. Implementation of the MIPS-III architecture results in 64-bit opera- tions, better code density, greater multi-processing support, improved performance for commonly used code sequences in operating system kernels and faster execution of floating-point intensive applications. All 0 47 TLB (entries protected from TLB W R ) EntryH i 10* EntryLo0 2* EntryLo1 3* PageMask 5* Wired 6* Random 1* Index 0* S tatus 12* Cause 13* EPC 14* ErrorEPC 30* C ount 9* Com pare 11* C ontext 4* XC ontext 20* PRId 15* Config 16* TagH i 29* TagLo 28* EC C 26* CacheErr 27* BadVAddr 8* LLA ddr 17* * Register number 3* resource dependencies are made transparent to the programmer, insuring transportability among implementations of the MIPS instruction set architecture. The MIPS integer unit implements a load/store architecture with single cycle ALU operations (logical, shift, add, sub) and an autono- mous multiply/divide unit. Register resources include: x 32 general-purpose orthogonal integer registers x HI/LO result registers, for the integer multiply/divide unit x Program counter Also, the on-chip floating-point co-processor adds 32 floating-point registers and a floating-point control/status register. Register File Register File Register File Register File The R4700 has 32 general-purpose registers (shown in Figure 2). These registers are used for scalar integer operations and address calculation. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. ALU ALU ALU ALU The RC4700 ALU consists of the integer adder and logic unit. The adder performs address calculations in addition to arithmetic operations, and the logic unit performs all logical and shift operations. Each of these units is highly optimized and can perform an operation in a single pipe- line cycle. Integer Multiply/Divide Integer Multiply/Divide Integer Multiply/Divide Integer Multiply/Divide To perform integer multiply and divide operations, the RC4700 uses the floating-point unit. The results of the operation are placed in the HI and LO registers. The values can then be transferred to the general purpose register file using the MFHI/MFLO instructions. To prevent the General Purpose Registers Multiply/Divide Registers 63 0 063 0 r1 HI r2 63 0 •LO • • Program Counter •63 0 r29 PC r30 r31 Figure 2 R4700 CPU Registers |
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