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IDT72T40108L10BBI Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT72T40108L10BBI Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 52 page  1 DECEMBER 2003 DSC-5995/8 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 2.5 VOLT HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40, 131,072 x 40 IDT72T4088, IDT72T4098 IDT72T40108, IDT72T40118 FEATURES ••••• Choose among the following memory organizations: IDT72T4088 16,384 x 40 IDT72T4098 32,768 x 40 IDT72T40108 65,536 x 40 IDT72T40118 131,072 x 40 • Up to 250MHz Operation of Clocks - 4ns read/write cycle time, 3.2ns access time • Users selectable input port to output port data rates, 500Mb/s Data Rate -DDR to DDR -DDR to SDR -SDR to DDR -SDR to SDR • User selectable HSTL or LVTTL I/Os • Read Enable & Read Clock Echo outputs aid high speed operation ••••• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage ••••• 3.3V Input tolerant • Mark & Retransmit, resets read pointer to user marked position • Write Chip Select (WCS) input enables/disables Write Operations • Read Chip Select (RCS) synchronous to RCLK • Programmable Almost-Empty and Almost-Full flags, each flag FUNCTIONAL BLOCK DIAGRAM can default to one of four preselected offsets • Dedicated serial clock input for serial programming of flag offsets • User selectable input and output port bus sizing -x40 in to x40 out -x40 in to x20 out -x40 in to x10 out -x20 in to x40 out -x10 in to x40 out • Auto power down minimizes standby power consumption • Master Reset clears entire FIFO • Partial Reset clears data, but retains programmable settings • Empty and Full flags signal FIFO status • Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) • Output enable puts data outputs into High-Impedance state • JTAG port, provided for Boundary Scan function • 208 Ball Grid array (PBGA), 17mm x 17mm, 1mm pitch • Easily expandable in depth and width • Independent Read and Write Clocks (permit reading and writing simultaneously) • High-performance submicron CMOS technology • Industrial temperature range (-40 °°°°°C to +85°°°°°C) is available INPUT REGISTER OUTPUT REGISTER RAM ARRAY 16,384 x 40, 32,768 x 40 65,536 x 40 131,072 x 40 FLAG LOGIC FF/IR PAF EF/OR PAE READ POINTER READ CONTROL LOGIC WRITE CONTROL LOGIC WRITE POINTER RESET LOGIC WEN WCLK D0 -Dn (x40, x20, x10) SREN MRS REN RCLK OE Q0 -Qn (x40, x20, x10) OFFSET REGISTER PRS FWFT SEN RT 5995 drw01 BUS CONFIGURATION OW FSEL0 FSEL1 IW MARK SCLK RCS JTAG CONTROL (BOUNDARY SCAN) TCK TMS TDO TDI TRST RSDR WCS ERCLK EREN HSTL I/0 CONTROL Vref HSTL BM WSDR SI SO |
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