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IDT72T40118L5BBI Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT72T40118L5BBI Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 52 page 7 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 PIN DESCRIPTION (CONTINUED) RCS Read Chip Select HSTL-LVTTL RCS provides synchronous enable/disable control of the read port and High-Impedance control of the (F14) INPUT Qn data outputs, synchronous to RCLK. When using RCS the OE pinmustbetiedLOW.DuringMaster or Partial Reset the RCS input is don’t care, if OE is LOW the data outputs will be Low-Impedance regardless of RCS. REN Read Enable HSTL-LVTTL When LOW and in DDR mode, REN along with a rising and falling edge of RCLK will send data in FIFO (F16) INPUT memory to the output register and read the current data in output register. In SDR mode data will only be read on the rising edge of RCLK only. RSDR(1) Read Single Data LVTTL WhenLOW,thisinputpinsetsthereadporttoSingleDataClockmode.WhenHIGH,thereadportwilloperate (L2) Rate INPUT inDoubleDataClockmode.ThispinmustbetiedeitherHIGHorLOWandcannottoggleduringoperation. RT Retransmit HSTL-LVTTL RTassertedontherisingedgeofRCLKinitializesthereadpointertothefirstlocationinmemory.EFflag (F15) INPUT is set to LOW ( OR to HIGH in FWFT mode). The write pointer, offset registers, and flag settings are not affected.IfamarkhasbeensetviatheMARKinputpin,thenthereadpointerwillinitializetothemarklocation when RT is asserted. SCLK Serial Clock LVTTL A rising edge of SCLK will clock the serial data present on the SI input into the offset registers provided (H15) INPUT that SENisenabled.ArisingedgeofSCLKwillalsoreaddataoutoftheoffsetregistersprovidedthatSREN is enabled. SEN Serial Input HSTL-LVTTL SEN used in conjunction with SI and SCLK enables serial loading of the programmable flag offsets. (J15) Enable INPUT SREN Serial Read HSTL-LVTTL SREN used in conjunction with SO and SCLK enables serial reading of the programmable flag offsets. (J16) Enable INPUT SI Serial Input HSTL-LVTTL This input pin is used to load serial data into the programmable flag offsets. Used in conjunction with SEN (H16) INPUT and SCLK. SO SerialOutput HSTL-LVTTL This output pin is used to read data from the programmable flag offsets. Used in conjunction with SREN (K15) OUTPUT and SCLK. TCK(2) JTAG Clock HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test (F1) INPUT operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND. TDI(2) JTAG Test Data HSTL-LVTTL OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation, (E2) Input INPUT testdataseriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegister and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected. TDO(2) JTAG Test Data HSTL-LVTTL OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation, (F3) Output OUTPUT test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT- DR and SHIFT-IR controller states. TMS(2) JTAG Mode HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the (F2) Select INPUT thedevicethroughitsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected. TRST(2) JTAG Reset HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not (E3) INPUT automatically reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles. If the TAP controller is not properly reset then the FIFO outputs will always be in high- impedance. If the JTAG function is used but the user does not want to use TRST,thenTRST canbetied with MRSto ensure proper FIFO operation. If the JTAG function is not used then this signal needs to be tied to GND. An internal pull-up resistor forces TRST HIGH if left unconnected. WCLK WriteClock HSTL-LVTTL Input clock when used in conjunction with WEN for writing data into the FIFO memory. (G1) INPUT WCS WriteChipSelect HSTL-LVTTL The WCS pin can be regarded as a second WEN input, enabling/disabling write operations. (H2) INPUT WEN WriteEnable HSTL-LVTTL When LOW and in DDR mode, WEN along with a rising and falling edge of WCLK will write data into the (H1) INPUT FIFO memory. In SDR mode data will only be read on the rising edge of RCLK only. Symbol & Name I/O TYPE Description Pin No. |
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