Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

IDT79RV4700-100-GH Datasheet(PDF) 7 Page - Integrated Device Technology

Part # IDT79RV4700-100-GH
Description  64-Bit RISC Microprocessor
Download  25 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT79RV4700-100-GH Datasheet(HTML) 7 Page - Integrated Device Technology

Back Button IDT79RV4700-100-GH Datasheet HTML 3Page - Integrated Device Technology IDT79RV4700-100-GH Datasheet HTML 4Page - Integrated Device Technology IDT79RV4700-100-GH Datasheet HTML 5Page - Integrated Device Technology IDT79RV4700-100-GH Datasheet HTML 6Page - Integrated Device Technology IDT79RV4700-100-GH Datasheet HTML 7Page - Integrated Device Technology IDT79RV4700-100-GH Datasheet HTML 8Page - Integrated Device Technology IDT79RV4700-100-GH Datasheet HTML 9Page - Integrated Device Technology IDT79RV4700-100-GH Datasheet HTML 10Page - Integrated Device Technology IDT79RV4700-100-GH Datasheet HTML 11Page - Integrated Device Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 25 page
background image
7 of 25
April 10, 2001
IDT79R4700
ValidOut* and ValidIn* are used by the RC4700 and the external
device respectively to indicate that there is a valid command or data on
the SysAD and SysCmd buses. The RC4700 asserts ValidOut* when it
is driving these buses with a valid command or data, and the external
device drives ValidIn* when it has control of the buses and is driving a
valid command or data.
Non-overlapping System Interface
Non-overlapping System Interface
Non-overlapping System Interface
Non-overlapping System Interface
The RC4700 bus uses a non-overlapping system interface. This
means that only one processor request may be outstanding at a time
and that the request must be serviced by an external device before the
RC4700 issues another request. The RC4700 can issue read and write
requests to an external device, and an external device can issue read
and write requests to the RC4700.
For processor read transaction the RC4700 asserts ValidOut* and
simultaneously drives the address and read command on the SysAD
and SysCmd buses. If the system interface has RdRdy* asserted, then
the processor tristates its drivers and releases the system interface to
slave state by asserting Release*. The external device can then begin
sending the data.
Figure 5 on page 10 shows a processor block read request and the
external agent read response. The read latency is four cycles (ValidOut*
to ValidIn*), and the response data pattern is DDxxDD. Figure 6 on
page 10 shows a processor block write.
Write Reissue and Pipeline Write
Write Reissue and Pipeline Write
Write Reissue and Pipeline Write
Write Reissue and Pipeline Write
The RC4700 implements additional write protocols that have been
designed to improve performance. This implementation doubles the
effective write bandwidth. The write re-issue has a high repeat rate of
two cycles per write. A write issues if WrRdy* is asserted two cycles
earlier and is still asserted at the issue cycle. If it is not still asserted, the
last write re-issues again. Pipelined writes have the same two cycle per
write repeat rate but can issue one additional write after WrRdy* de-
asserts. They still follow the issue rule as R4x00 mode for other writes.
External Requests
External Requests
External Requests
External Requests
The RC4700 responds to requests issued by an external device. The
requests can take several forms. An external device may need to supply
data in response to an RC4700 read request or it may need to gain
control over the system interface bus to access other resources which
may be on that bus. It also may issue requests to the processor, such as
a request for the RC4700 to write to the RC4700 interrupt register. The
RC4700 supports Write, Null, and Read Response external requests.
Boot-Time Options
Boot-Time Options
Boot-Time Options
Boot-Time Options
Fundamental operational modes for the processor are initialized by
the boot-time mode control interface. The boot-time mode control inter-
face is a serial interface operating at a very low frequency (MasterClock
divided by 256). The low-frequency operation allows the initialization
information to be kept in a low-cost serial EEPROM; alternatively, the
20-or-so bits could be generated by the system interface ASIC or a
simple PAL.
Immediately after the VCCOK signal is asserted, the processor reads a
bit stream of 256 bits to initialize all fundamental operational modes.
After initialization is complete, the processor continues to drive the serial
clock output, but no further initialization bits are read.
JTAG Interface
JTAG Interface
JTAG Interface
JTAG Interface
The RC4700 supports the JTAG interface pins, with the serial input
connected to serial output. Boundary scan is not supported.
Boot-Time Modes
Boot-Time Modes
Boot-Time Modes
Boot-Time Modes
The boot-time serial mode stream is defined in Table 3. Bit 0 is the
first bit presented to the processor when VCCOK is asserted; bit 255 is the
last.
Power Management
Power Management
Power Management
Power Management1111
CP0 is also used to control the power management for the RC4700.
This is the standby mode and can be used to reduce the power
consumption of the internal core of the CPU. Standby mode is entered
by executing the WAIT instruction with the SysAD bus idle and is exited
by an interrupt.
Standby Mode Operations
Standby Mode Operations
Standby Mode Operations
Standby Mode Operations
The RC4700 provides a means to reduce the amount of power
consumed by the internal core when the CPU would otherwise not be
performing any useful operations. This is known as “Standby Mode.”
Entering Standby Mode
Entering Standby Mode
Entering Standby Mode
Entering Standby Mode
Executing the WAIT instruction enables interrupts and enters
Standby mode. When the WAIT instruction finishes the W pipe-stage, if
the SysAd bus is currently idle, the internal clocks will shut down, thus
freezing the pipeline. The PLL, internal timer, some of the input pin
clocks (Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*), and the
output clocks—TClock[1:0], RClock[1:0] SyncOut, Modeclock and
MasterOut—will continue to run. If the conditions are not correct when
the WAIT instruction finishes the W pipe-stage (such as the SysAd bus
is not idle), the WAIT is treated as a NOP.
Once the CPU is in Standby Mode, any interrupt— including the
internally generated timer interrupt—will cause the CPU to exit Standby
Mode.
1. The R4700 implements advanced power management, to substantially
reduce the average power dissipation of the device. This operation is described
in the R4700 Microprocessor Hardware User’s Manual.


Similar Part No. - IDT79RV4700-100-GH

ManufacturerPart #DatasheetDescription
logo
Integrated Device Techn...
IDT79RV4640-100DU IDT-IDT79RV4640-100DU Datasheet
205Kb / 23P
   Low-Cost Embedded 64-bit RISController w/ DSP Capability
IDT79RV4640-100DUI IDT-IDT79RV4640-100DUI Datasheet
205Kb / 23P
   Low-Cost Embedded 64-bit RISController w/ DSP Capability
IDT79RV4640-100DZ IDT-IDT79RV4640-100DZ Datasheet
205Kb / 23P
   Low-Cost Embedded 64-bit RISController w/ DSP Capability
IDT79RV4640-100DZI IDT-IDT79RV4640-100DZI Datasheet
205Kb / 23P
   Low-Cost Embedded 64-bit RISController w/ DSP Capability
IDT79RV4640-100MU IDT-IDT79RV4640-100MU Datasheet
205Kb / 23P
   Low-Cost Embedded 64-bit RISController w/ DSP Capability
More results

Similar Description - IDT79RV4700-100-GH

ManufacturerPart #DatasheetDescription
logo
Renesas Technology Corp
IDT79R4700 RENESAS-IDT79R4700 Datasheet
984Kb / 26P
   64-Bit RISC Microprocessor
December 5, 2008
logo
Integrated Device Techn...
IDT79R4700 IDT-IDT79R4700_08 Datasheet
785Kb / 25P
   64-Bit RISC Microprocessor
logo
Toshiba Semiconductor
TMPR4925XB TOSHIBA-TMPR4925XB Datasheet
151Kb / 32P
   64-bit RISC MICROPROCESSOR
logo
PMC-Sierra, Inc
RM5231A PMC-RM5231A Datasheet
54Kb / 4P
   64-Bit MIPS RISC Microprocessor with 32/64-Bit System Bus
RM5231A-1 PMC-RM5231A-1 Datasheet
39Kb / 2P
   64-Bit MIPS RISC Microprocessor with 32/64-Bit System Bus
RM7000A PMC-RM7000A Datasheet
52Kb / 4P
   64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
RM7065A PMC-RM7065A Datasheet
52Kb / 4P
   64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
RM7000A-1 PMC-RM7000A-1 Datasheet
38Kb / 2P
   64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
RM7000B PMC-RM7000B Datasheet
36Kb / 2P
   64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
RM7065A-1 PMC-RM7065A-1 Datasheet
38Kb / 2P
   64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com