 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
COP8780CV Datasheet(PDF) 7 Page - National Semiconductor (TI) |
|
|
||||||||||||||||||||||||||||||
COP8780CV Datasheet(HTML) 7 Page - National Semiconductor (TI) |
|
|
7 / 28 page  Functional Description (Continued) TABLE II Crystal Oscillator Configuration TA e 25 C R1 R2 C1 C2 CKI Freq Conditions (kX)(MX) (pF) (pF) (MHz) 0 1 30 30 – 36 10 VCC e 5V 0 1 30 30 – 36 4 VCC e 5V TABLE III RC Oscillator Configuration TA e 25 C R C CKI Freq Instr Cycle Conditions (kX) (pF) (MHz) (ms) 33 82 22 to 27 37 to 46 VCC e 5V 56 100 11 to 13 74 to 90 VCC e 5V 68 100 09 to 11 88 to 108 VCC e 5V Note (RC Oscillator Configuration) 3k s R s 200k 50 pF s C s 200 pF C RC Oscillator CKI can be configured as a single pin RC controlled oscilla- tor In RC oscillator mode G7 is available as a general pur- pose input andor HALT restart control Table III shows the variation in the oscillator frequencies as functions of the component (R and C) values HALT MODE The device supports a power saving mode of operation HALT The controller is placed in the HALT mode by setting the G7 data bit alternatively the user can stop the clock input (Stopping the clock input will draw more current than setting the G7 data bit) In the HALT mode all internal proc- essor activities including the clock oscillator are stopped The fully static architecture freezes the state of the control- ler and retains all information until continuing In the HALT mode power requirements are minimal as it draws only leakage currents and output current The applied voltage (VCC) may be decreased down to Vr (minimum RAM reten- tion voltage) without altering the state of the machine There are two ways to exit the HALT mode via the RESET or by the G7 pin A low on the RESET line reinitializes the microcontroller and starts execution from address 0000H In external and RC oscillator modes a low to high transition on the G7 pin also causes the microcontroller to come out of the HALT mode Execution resumes at the address follow- ing the HALT instruction Except for the G7 data bit which gets reset all RAM locations retain the values they had prior to execution of the ‘‘HALT’’ instruction It is required that the first instruction following the ‘‘HALT’’ instruction be a ‘‘NOP’’ in order to synchronize the clock INTERRUPTS The device has a sophisticated interrupt structure to allow easy interface to the real world There are three possible interrupt sources as shown below A maskable interrupt on external G0 input (positive or nega- tive edge sensitive under software control) A maskable interrupt on timer underflow or timer capture A non-maskable softwareerror interrupt on opcode zero INTERRUPT CONTROL The GIE (global interrupt enable) bit enables the interrupt function This is used in conjunction with ENI and ENTI to select one or both of the interrupt sources This bit is reset when interrupt is acknowledged ENI and ENTI bits select external and timer interrupts re- spectively Thus the user can select either or both sources to interrupt the microcontroller when GIE is enabled IEDG selects the external interrupt edge (0 e rising edge 1 e falling edge) The user can get an interrupt on both rising and falling edges by toggling the state of IEDG bit after each interrupt IPND and TPND bits signal which interrupt is pending After an interrupt is acknowledged the user can check these two bits to determine which interrupt is pending This permits the interrupts to be prioritized under software The pending flags have to be cleared by the user Setting the GIE bit high inside the interrupt subroutine allows nested interrupts The software interrupt does not reset the GIE bit This means that the controller can be interrupted by other inter- rupt sources while servicing the software interrupt INTERRUPT PROCESSING The interrupt once acknowledged pushes the program counter (PC) onto the stack and the stack pointer (SP) is decremented twice The Global Interrupt Enable (GIE) bit is reset to disable further interrupts The microcontroller then vectors to the address 00FFH and resumes execution from that address This process takes 7 cycles to complete At the end of the interrupt subroutine any of the following three instructions return the processor back to the main pro- gram RET RETSK or RETI Either one of the three instruc- tions will pop the stack into the program counter (PC) The stack pointer is then incremented twice The RETI instruc- tion additionally sets the GIE bit to re-enable further inter- rupts Any of the three instructions can be used to return from a hardware interrupt subroutine The RETSK instruction should be used when returning from a software interrupt subroutine to avoid entering an infinite loop Note There is always the possiblity of an interrupt occurring during an in- struction which is attempting to reset the GIE bit or any other interrupt enable bit If this occurs when a single cycle instruction is being used to reset the interrupt enable bit the interrupt enable bit will be reset but an interrupt may still occur This is because interrupt processing is started at the same time as the interrupt bit is being reset To avoid this scenario the user should always use a two three or four cycle instruction to reset interrupt enable bits http www nationalcom 7 |
Similar Part No. - COP8780CV |
|
Similar Description - COP8780CV |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
