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ADT7302 Datasheet(PDF) 5 Page - Analog Devices

Part No. ADT7302
Description  Accurate, Micropower Digital Accurate, Micropower Digital
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADT7302 Datasheet(HTML) 5 Page - Analog Devices

 
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ADT7302
Rev. B | Page 4 of 16
TIMING CHARACTERISTICS
Guaranteed by design and characterization, not production tested. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD)
and timed from a voltage level of 1.6 V.
TA = TMIN to TMAX, VDD = 2.7 V to 5.25 V, unless otherwise noted.
Table 2.
Parameter1
Limit
Unit
Comments
t
1
5
ns min
CS to SCLK setup time
t
2
25
ns min
SCLK high pulse width
t
3
25
ns min
SCLK low pulse width
t
4
2
35
ns max
Data access time after SCLK falling edge
t
5
20
ns min
Data setup time prior to SCLK rising edge
t
6
5
ns min
Data hold time after SCLK rising edge
t
7
5
ns min
CS to SCLK hold time
t
8
2
40
ns max
CS to DOUT high impedance
1 See Figure 14 for the SPI timing diagram.
2 Measured with the load circuit of Figure 2.
1.6V
200
µA
200
µA
IOH
IOL
TO
OUTPUT
PIN
CL
50pF
Figure 2. Load Circuit for Data Access Time and Bus Relinquish Time


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