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ADE9000 Datasheet(PDF) 31 Page - Analog Devices |
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ADE9000 Datasheet(HTML) 31 Page - Analog Devices |
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31 / 73 page  ADE9000 Data Sheet Rev. A | Page 30 of 72 Digital to Frequency Conversion—CFx Output The ADE9000 includes four pulse outputs that are proportional to the energy accumulation in the CF1 through CF4 output pins. Figure 66 shows a block diagram of the CFx pulse generation. CF3 is multiplexed with ZX, and CF4 is multiplexed with EVENT and DREADY. Energy and Phase Select ion The CFxSEL bits in the CFMODE register select which type of energy to output on the CFx pins. The TERMSELx bits in the COMPMODE register select which phase energies to include in the CFx output. For example, with CF1SEL = 000 and TERMSEL1 = 111, CF1 indicates the total active power output of Phase A, Phase B, and Phase C. Configuring the CFx Pulse Width The value of the CFx_LT and the CF_LTMR bits in the CF_LCFG register determines the pulse width. The maximum CFx with threshold (xTHR) = 0x00100000 and CFxDEN = 2 is 78.9 kHz. It is recommended to have xTHR = 0x00100000. CFx Pulse Sign The SUMxSIGN bits in the PHSIGN register indicate whether the sum of the energy that went into the last CFx pulse is positive or negative. The REVPSUMx bits in the STATUS0 register and the EVENT_STATUS register indicate if the CFx polarity changed sign. This feature generates an interrupt on IRQ0. Clearing the CFx Accumulator To clear the accumulation in the digital to frequency converter and CFDEN counter, write 1 to the CF_ACC_CLR bit in the CONFIG1 register. The CF_ACC_CLR bit automatically clears itself. fDSP xWATT xVAR xVA xFVAR xFVA xWATT xWATT CFxSEL 100 011 000 001 010 101 110 xWATT 111 TERMSELx PHASE A TERMSELx PHASE B TERMSELx + + + CFxSEL WTHR CFx_LT CF_LTMR CFxDIS 4.096MHz DIGITAL TO FREQUENCY 512 CFxDEN CF_ACC_CLR CFx PIN PULSE WIDTH CONFIGURATION ADE9000 CFx BITS PHASE C VARTHR VATHR WTHR VARTHR VATHR WTHR WTHR 100 011 000 001 010 101 110 111 ÷ Figure 66. Digital to Frequency Conversion for CFx |
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