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ADE9000 Datasheet(PDF) 28 Page - Analog Devices |
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ADE9000 Datasheet(HTML) 28 Page - Analog Devices |
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28 / 73 page  Data Sheet ADE9000 Rev. A | Page 27 of 72 IB Calculation Using ICONSEL Write to the ICONSEL bit in the ACCMODE register to calculate IB = −IA − IC. This setting can help save the cost of a current transformer in some 3-wire delta configurations. High-Pass Filter A high-pass filter removes dc offsets for accurate rms and energy measurements. It is enabled by default with a corner frequency is 1.25 Hz. To disable the high-pass filter on all current and voltage channels set the HPFDIS bit in the CONFIG0 register. The corner frequency is configured with the HPF_CRN bits in the CONFIG2 register. Digital Integrator A digital integrator is included to allow easy interfacing to di/dt current sensors, also known as Rogowski coils. To configure the digital integrator use the INTEN and ININTEN bits in the CONFIG0 register. It is disabled by default. If the integrator is enabled, set the DICOEFF value to 0xFFFFE000. Phase Compensation The ADE9000 provides a phase compensation register for each current channel: APHCALx, BPHCALx, CPHCALx, and NPHCAL. The phase calibration range is −15° to +2.25° at 50 Hz and −15° to +2.7° at 60 Hz. Use the following equation to calculate the xPHCALx value for a given phase correction (φ)° angle. Phase correction (φ)° is positive to correct a current that lags the voltage, and negative to correct a current that leads the voltage, as seen in a current transformer. ( ) ( ) 27 2 – 2 sin sin – sin × ϕ ω ω + ω ϕ = xPHCALx ω = 2π × fLINE/fDSP where: fLINE is the line frequency. fDSP is 8 kHz. Multipoint Phase and Gain Calibration The ADE9000 allows multipoint gain and phase compensation with hysteresis on the IA, IB, and IC current channels. The current channel gain and phase compensation vary as a function of the calculated input current rms amplitude in xIRMS. There are five gain registers (xIGAIN0 to xIGAIN4) and five phase calibration registers (xPHCAL0 to xPHCAL4) for each channel. Set the MTEN bit in the CONFIG0 register to enable multipoint gain and phase calibration. MTEN = 0 by default. The gain and phase calibration factor is applied based on the xIRMS current amplitude and the MTTHR_Lx and the MTTHR_Hx register values, as shown in Figure 59. IRMS GAIN, PHASE CORRECTION MTTHR_L1 , MTTHR_H0 MTTHR_H4 = FULL SCALE MTTHR_L0 = 0 REGION 0 REGION 1 REGION 2 REGION 3 REGION 4 MTTHR_L2, MTTHR_H1 MTTHR_L3, MTTHR_H2 MTTHR_L4, MTTHR_H3 xIGAIN4 xPHCAL4 xIGAIN3 xPHCAL3 xIGAIN2 xPHCAL2 xIGAIN1 xPHCAL1 xIGAIN0 xPHCAL0 X X X X X Figure 59. Multipoint Phase and Gain Calibration Voltage Channel The ADE9000 has three voltage channels. The datapaths for the VA, VB, and VC voltage channels is shown in Figure 60. The xVGAIN registers calibrate the voltage channel of each phase. The xVGAIN registers have the same scaling as the xIGAIN registers. RMS and Power Measurements The ADE9000 calculates total and fundamental values of rms current, rms voltage, active power, reactive power, and apparent power. The fundamental algorithm requires initialization of the network frequency using the SELFREQ bit in the ACCMODE register and the nominal voltage in the VLEVEL register. Calculate VLEVEL value according to the following equation: VLEVEL = x × 1,444,084 where x is the dynamic range that the nominal input signal is at with respect to full scale. For instance, if the signal is at ½ of full scale, x = 2. VLEVEL = 2 × 1,444,084 REFERENCE Σ-Δ MODULATOR VP VIN VM SINC4 LPF 4:1 xVGAIN PHASE COMP WAVEFORM BUFFER WF_SRC HPFDIS ZX_SRC_SEL VCONSEL1 VB = VA – VC WF_CAP_SEL xV_PCF 000 001 VB = –VA – VC VB = – VA VA = VA – VB; VB = VA – VC; VC = VC – VB; 100 011 010 ADC_ REDIRECT MUX RMS_SRC_SEL FAST RMS½, 10 CYCLE RMS/ 12 CYCLE RMS RESAMPLING 1VCONSEL SUPPORTS SEVERAL 3-WIRE AND 4-WIRE HARDWARE CONFIGURATIONS. ZERO-CROSSING DETECTION FUNDAMENTAL AND TOTAL ACTIVE AND REACTIVE POWER CALCULATIONS VOLTAGE PEAK DETECTION FUNDAMENTAL AND TOTAL RMS, VA, THD CALCULATIONS HPF Figure 60. Voltage Channel Datapath |
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