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MC908GR4MDWR2 Datasheet(PDF) 93 Page - Motorola, Inc |
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MC908GR4MDWR2 Datasheet(HTML) 93 Page - Motorola, Inc |
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93 / 408 page  Break Module (BRK) Functional Description MC68HC908GR8 — Rev 4.0 Technical Data MOTOROLA Break Module (BRK) 93 6.4.1 Flag Protection During Break Interrupts The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. 6.4.2 CPU During Break Interrupts The CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) Addr. Register Name Bit 7 654321 Bit 0 $FE00 SIM Break Status Register (SBSR) Read: 000100 BW 0 Write: RRRRRR NOTE R Reset: 00010000 $FE03 SIM Break Flag Control Register (SBFCR) Read: BCFE RRRRRRR Write: Reset: 0 $FE09 Break Address Register High (BRKH) Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Reset: 00000000 $FE0A Break Address Register Low (BRKL) Read: Bit 7 654321 Bit 0 Write: Reset: 00000000 $FE0B Break Status and Control Register (BRKSCR) Read: BRKE BRKA 000000 Write: Reset: 00000000 Note: Writing a logic 0 clears BW. = Unimplemented R = Reserved Figure 6-2. I/O Register Summary Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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