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AD9736BBC Datasheet(PDF) 4 Page - Analog Devices |
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AD9736BBC Datasheet(HTML) 4 Page - Analog Devices |
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4 / 42 page  AD9736/AD9735/AD9734 Preliminary Technical Data Rev. PrJ | Page 4 of 42 DIGITAL SPECIFICATIONS1 (VDDA33 = VDDD33 = 3.3 V, VDDA18 = VDDD18 = VDDCLK = 1.8 V, MAXIMUM SAMPLE RATE, FS = 20MA, 1X MODE, 25 OHM 1% BALANCED LOAD, UNLESS OTHERWISE NOTED) AD9736,35,34 Parameter Temp Test Level Min Typ Max Unit Input voltage range, Via or Vib 825 1575 mV Input differential threshold -100 100 mV Input differential hysteresis 20 mV Receiver differential input impedance 80 120 Ω LVDS input rate 1200 MSPS LVDS DATA INPUTS (DB[13:0]+, DB[13:0]-) DB+ = Via, DB- = Vib LVDS data Bit Error Rate TBD Err/Bit Input voltage range, Via or Vib 825 1575 mV Input differential threshold -100 100 mV Input differential hysteresis 20 mV Receiver differential input impedance 80 120 Ω LVDS CLOCK INPUT (DATACLK_IN+, DATACLK_IN-) DATACLK+ = Via, DATACLK- = Vib Maximum Clock Rate 600 MHz Output voltage high, Voa or Vob 1375 mV Output voltage low, Voa or Vob 1025 mV Output differential voltage 150 200 250 mV Output offset voltage 1150 1250 mV Output impedance, single ended 80 100 120 Ω Ro mismatch between A & B 10 % Change in |Vod| between ‘0’ and ‘1’ 25 mV Change in Vos between ‘0’ and ‘1’ 25 mV Output current – Driver shorted to ground 20 mA Output current – Drivers shorted together 4 mA Power-off output leakage TBD mA LVDS CLOCK OUTPUT (DATACLK_OUT+, DATACLK_ OUT-) DATACLK_OUT+ = Voa, DATACLK_OUT- = Vob 100 ohm termination Maximum Clock Rate 600 MHz Differential peak-to-peak Voltage 800 mV Common Mode Voltage 400 mV DAC CLOCK INPUT (CLK+, CLK-) Maximum Clock Rate 1200 MHz Maximum Clock Rate (SCLK, 1/tSCLK) 20 MHz Minimum pulse width high, tPWH 20 ns Minimum pulse width low, tPWL 20 ns Minimum SDIO and CSB to SCLK setup, tDS 10 ns Minimum SCLK to SDIO hold, tDH 5 ns Maximum SCLK to valid SDIO and SDO, tDV 20 ns SERIAL PERIPHERAL INTERFACE Minimum SCLK to invalid SDIO and SDO, tDNV 5 ns Table 2: Digital Specifications 1 LVDS Drivers and Receivers are compliant to the IEEE-1596 Reduced Range Link, unless otherwise noted |
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