AD73322LAST-REEL datasheet(22/49 Pages) AD

Part #	AD73322LAST-REEL

Description	Low Cost, Low Power CMOS General-Purpose Dual Analog Front

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Manufacturer	AD [Analog Devices]

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AD73322L

Rev. A | Page 21 of 48

CONTROL REGISTER A

Table 18. Control Register A Description

7

6

5

4

3

2

1

0

RESET

DC2

DC1

DC0

SLB

BLB

MM

DATA/PGM

Bit

Name

Description

0

DATA/PGM

Operating Mode (0 = program; 1 = data mode)

1

MM

Mixed Mode (0 = off; 1 = enabled)

2

DLB

Digital Loop-Back Mode (0 = off; 1 = enabled)

3

SLB

SPORT Loop-Back Mode (0 = off; 1 = enabled)

4

DC0

Device Count (Bit 0)

5

DC1

Device Count (Bit 1)

6

DC2

Device Count (Bit 2)

7

RESET

Software Reset (0 = off; 1 = initiates reset)

CONTROL REGISTER B

Table 19. Control Register B Description

7

6

5

4

3

2

1

0

CEE

MCD2

MCD1

MCD0

SCD1

SCD0

DIR1

DIR0

Bit

Name

Description

0

DIR0

Decimation/Interpolation Rate (Bit 0)

1

DIR1

Decimation/Interpolation Rate (Bit 1)

2

SCD0

Serial Clock Divider (Bit 0)

3

SCD1

Serial Clock Divider (Bit 1)

4

MCD0

Master Clock Divider (Bit 0)

5

MCD1

Master Clock Divider (Bit 1)

6

MCD2

Master Clock Divider (Bit 2)

7

CEE

Control Echo Enable (0 = off; 1 = enabled)

CONTROL REGISTER C

Table 20. Control Register C Description

7

6

5

4

3

2

1

0

—

RU

PUREF

PUDAC

PUADC

PUIA

PUAGT

PU

Bit

Name

Description

0

PU

Power-Up Device (0 = power-down; 1 = power on)

1

PUAGT

Analog Gain Tap Power (0 = power-down; 1 = power on)

2

PUIA

Input Amplifier Power (0 = power-down; 1 = power on)

3

PUADC

ADC Power (0 = power-down; 1 = power on)

4

PUDAC

DAC Power (0 = power-down; 1 = power on)

5

PUREF

REF Power (0 = power-down; 1 = power on)

6

RU

REFOUT Use (0 = disable REFOUT; 1 = enable REFOUT)

7

—

Reserved, must be programmed to 0

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AD73322LAST-REEL Datasheet(PDF) 22 Page - Analog Devices

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