AD73322LARU-REEL datasheet(30/49 Pages) AD

Part #	AD73322LARU-REEL

Description	Low Cost, Low Power CMOS General-Purpose Dual Analog Front

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AD73322L

Rev. A | Page 29 of 48

PERFORMANCE

Because the AD73322L is designed to provide high perfor-

mance and low cost conversion, it is important to understand

how high performance can be achieved in a typical application.

By means of spectral graphs, this section outlines the typical

performance of the device and highlights some of the options

available to users in achieving their desired sample rate, either

directly in the device or by doing some post-processing in the

DSP, while also showing the advantages and disadvantages of

the different approaches.

ENCODER SECTION

The AD73322L offers a variable sampling rate from a fixed

MCLK frequency—with 64 kHz, 32 kHz, 16 kHz, and 8 kHz

being available with a 16.384 MHz external clock. Each of

these sampling rates preserves the same sampling rate in the

ADC’s sigma-delta modulator, which ensures that the noise

performance is optimized in each case. The examples that

follow show the performance of a 1 kHz sine wave when

converted at the various sample rates.

The range of sampling rates is aimed to offer the user a degree

of flexibility in deciding how the analog front end is to be

implemented. The high sample rates of 64 kHz and 32 kHz are

suited to those applications, such as active control, where low

conversion group delay is essential. On the other hand, the

lower sample rates of 16 kHz and 8 kHz are better suited for

applications such as telephony, where the lower sample rates

result in lower DSP overhead.

Figure 29 shows the spectrum of the 1 kHz test tone sampled

at 64 kHz. The plot shows the characteristic shaped noise floor

of a sigma-delta converter, which is initially flat in the band of

interest but then rises with increasing frequency. If a suitable

digital filter is applied to this spectrum, the noise floor can be

eliminated in the higher frequencies. This signal can then be

used in DSP algorithms or can be further processed in a

decimation algorithm to reduce the effective sample rate.

Figure 26 shows the resulting spectrum following the filtering

and decimation of the spectrum of Figure 25 from 64 kHz to

an 8 kHz rate.

The AD73322L also features direct sampling at the lower rate of

8 kHz. This is achieved by the use of extended decimation

registers within the decimator block, which allows for the

increased word growth associated with the higher effective

oversampling ratio. Figure 27 details the spectrum of a 1 kHz

test tone converted at an 8 kHz rate.

The device features an on-chip, master clock divider circuit that

allows the sample rate to be reduced because the sampling rate

of the sigma-delta converter is proportional to the output of the

MCLK Divider (whose default state is divide-by-one).

The decimator’s frequency response (Sinc3) gives some pass-

band attenuation (up to FS/2) which continues to roll off above

the Nyquist frequency. If it is required to implement a digital

filter to create a sharper cutoff characteristic, it may be prudent

to use an initial sample rate of greater than twice the Nyquist

rate in order to avoid aliasing due to the smooth roll-off of the

sinc3 filter response.

FREQUENCY (Hz)

×104

3.5

0

0.5

1.0

1.5

2.0

2.5

3.0

0

–40

–20

–60

–80

–100

–120

–140

Figure 25. FFT (ADC 64 kHz Sampling)

FREQUENCY (Hz)

4000

0

500

1000

1500

2000

2500

3000

3500

0

–20

–40

–60

–80

–100

–120

Figure 26. FFT (ADC 8 kHz Filtered and Decimated from 64 kHz)

FREQUENCY (Hz)

4000

0

500

1000

1500

2000

2500

3000

3500

0

50

100

150

Figure 27. FFT (ADC 8 kHz Direct Sampling)

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