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ST72324BLK4 Datasheet(PDF) 55 Page - STMicroelectronics |
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ST72324BLK4 Datasheet(HTML) 55 Page - STMicroelectronics |
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55 / 151 page  ST72F324L, ST72324BL 55/151 16-BIT TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they re- turn the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, out- put compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: – The TOF bit of the SR register is set. – A timer interrupt is generated if: – TOIE bit of the CR1 register is set and – I bit of the CC register is cleared. If one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Notes: The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with- out the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset). 10.3.3.2 External Clock The external clock (where available) is selected if CC0=1 and CC1=1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the exter- nal clock pin EXTCLK that will trigger the free run- ning counter. The counter is synchronized with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock fre- quency must be less than a quarter of the CPU clock frequency. is buffered Read At t0 Read Returns the buffered LS Byte value at t0 At t0 + ∆t Other instructions Beginning of the sequence Sequence completed LS Byte LS Byte MS Byte 1 |
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