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ST72324BLJ4 Datasheet(PDF) 24 Page - STMicroelectronics |
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ST72324BLJ4 Datasheet(HTML) 24 Page - STMicroelectronics |
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24 / 151 page  ST72F324L, ST72324BL 24/151 6.3 RESET SEQUENCE MANAGER (RSM) 6.3.1 Introduction The reset sequence manager includes two RE- SET sources as shown in Figure 12: ■ External RESET source pulse ■ Internal WATCHDOG RESET These sources act on the RESET pin and it is al- ways kept low during the delay phase. The RESET service routine vector is fixed at ad- dresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 11: ■ Active Phase depending on the RESET source ■ 256 or 4096 CPU clock cycle delay (selected by option byte) ■ RESET vector fetch The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application. The RESET vector fetch phase duration is 2 clock cycles. Figure 11. RESET Sequence Phases 6.3.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in ac- cordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized. This detection is asynchro- nous and therefore the MCU can enter reset state even in HALT mode. The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteris- tics section. 6.3.3 External Power-On RESET To start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. A proper reset signal for a slow rising VDD supply can generally be provided by an external RC net- work connected to the RESET pin. 6.3.4 Internal Watchdog RESET Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. Figure 12. Reset Block Diagram RESET Active Phase INTERNAL RESET 256 or 4096 CLOCK CYCLES FETCH VECTOR RESET RON VDD WATCHDOG RESET INTERNAL RESET PULSE GENERATOR Filter 1 |
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