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STK15C88 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers

Part No. STK15C88
Description  32K x 8 AutoStore nvSRAM High Performance CMOS Nonvolatile Static RAM
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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STK15C88 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers

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STK15C88
August 1998
5-37
SRAM READ CYCLES #1 & #2
(Vcc = 5.0V ± 10%)
Note f:
W must be high during SRAM read cycles and low during SRAM write cycles.
Note g:
I/O state assumes E, G, < VIL and W > VIH; device is continuously selected
Note h:
Measured + 200mV from steady state output voltage
SRAM READ CYCLE #1 (Address Controlled)f, g
SRAM READ CYCLE #2 (E Controlled)f
NO.
SYMBOLS
PARAMETER
STK15C88-25
STK15C88-35
STK15C88-45
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1tELQV
tACS
Chip Enable Access Time
25
35
45
ns
2tAVAV
f
tRC
Read Cycle Time
25
35
45
ns
3tAVQV
g
tAA
Address Access Time
25
35
45
ns
4tGLQV
tOE
Output Enable to Data Valid
10
15
20
ns
5tAXQX
g
tOH
Output Hold After Address Change
3
3
3
ns
6tELQX
tLZ
Chip Enable to Output Active
5
5
5
ns
7tEHQZ
h
tHZ
Chip Disable to Output Inactive
10
13
15
ns
8tGLQX
tOLZ
Output Enable to Output Active
0
0
0
ns
9tGHQZ
h
tOHZ
Output Disable to Output Inactive
10
13
15
ns
10
tELICCH
e
tPA
Chip Enable to Power Active
0
0
0
ns
11
tEHICCL
d, e
tPS
Chip Disable to Power Standby
25
35
45
ns
DATA VALID
5
tAXQX
3
tAVQV
DQ(Data Out)
ADDRESS
2
tAVAV
6
tELQX
STANDBY
DATA VALID
8
tGLQX
4
tGLQV
DQ(Data Out)
E
ADDRESS
2
tAVAV
G
ICC
ACTIVE
1
tELQV
10
tELICCH
11
tEHICCL
7
tEHQZ
9
tGHQZ


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