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ST92F120V9 Datasheet(PDF) 50 Page - STMicroelectronics |
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ST92F120V9 Datasheet(HTML) 50 Page - STMicroelectronics |
50 / 324 page 50/324 ST92F120 - SINGLE VOLTAGE FLASH & EEPROM 3.6 PROTECTION STRATEGY The protection bits are stored in the last 4 loca- tions of the TestFlash (from 231FFCh) (see Figure 25). All the available protections are forced active dur- ing reset, then in the initialisation phase they are read from the TestFlash. The protections are stored in 2 Non Volatile Regis- ters. Other 2 Non Volatile Registers can be used as a password to re-enable test modes once they have been disabled. The protections can be programmed using the Set Protection operation (see Control Registers para- graph), that can be executed from all the internal or external memories except the Flash or Test- Flash itself. The TestFlash area (230000h to 231F7Fh) is al- ways protected against write access. Figure 25. Protection Map 3.6.1 Non Volatile Registers The 4 Non Volatile Registers used to store the pro- tection bits for the different protection features are one time programmable by the user, but they are erasable in Test mode (if not disabled). Access to these registers is controlled by the pro- tections related to the TestFlash where they are mapped. Since the code to program the Protection Registers cannot be fetched by the Flash or the TestFlash memories, this means that, once the APRO or APBR bits in the NVAPR register are programmed, it is no longer possible to modify any of the protection bits. For this reason the NV Pass- word, if needed, must be set with the same Set Protection operation used to program these bits. For the same reason it is strongly advised to never program the WPBR bit in the NVWPR register, as this will prevent any further write access to the TestFlash, and consequently to the Protection Registers. NON VOLATILE ACCESS PROTECTION REG- ISTER (NVAPR) Address: 231FFCh - Read/Write Delivery value: 1111 1111 (FFh) Bit 7 = Reserved. Bit 6 = APRO: Flash Access Protection. This bit, if programmed at 0, disables any access (read/write) to operands mapped inside the Flash address space (EEPROM excluded), unless the current instruction is fetched from the TestFlash or from the Flash itself. 0: Flash protection on 1: Flash protection off Bit 5 = APBR: TestFlash Access Protection. This bit, if programmed at 0, disables any access (read/write) to operands mapped inside the Test- Flash address space, unless the current instruc- tion is fetched from the TestFlash itself. 0: TestFlash protection on 1: TestFlash protection off Bit 4 = APEE: EEPROM Access Protection. This bit, if programmed at 0, disables any access (read/write) to operands mapped inside the EEP- ROM address space, unless the current instruc- tion is fetched from the TestFlash or from the Flash, or from the EEPROM itself. 0: EEPROM protection on 1: EEPROM protection off Bit 3 = APEX: Access Protection from External Memory. This bit, if programmed at 0, disables any access (read/write) to operands mapped inside the ad- dress space of one of the internal memories (Test- Flash, Flash, EEPROM, RAM), if the current in- struction is fetched from an external memory. NVAPR NVWPR 231FFCh 231FFDh Protection 231FFEh NVPWD0 NVPWD1 231FFFh 7 654 32 10 1 APRO APBR APEE APEX PWT2 PWT1 PWT0 9 |
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