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SCN2652AC2F40 Datasheet(PDF) 3 Page - NXP Semiconductors |
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SCN2652AC2F40 Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 28 page Philips Semiconductors Product specification SCN2652/SCN68652 Multi-protocol communications controller (MPCC) 1995 May 01 3 ORDERING CODE VCC = 5V +5% PACKAGES Commercial 0 °C to +70°C Industrial -40 °C to +85°C DWG # 40-Pin Ceramic Dual In-Line Package (DIP) SCN2652AC2F40 / SCN68652AC2F40 0590B 40-Pin Plastic Dual In-Line Package (DIP) SCN2652AC2N40 / SCN68652AC2N40 Contact Factory SOT129-1 44-Pin Square Plastic Lead Chip Carrier (PLCC) SCN2652AC2A44 / SCN68652AC2A44 Contact Factory SOT187-2 ABSOLUTE MAXIMUM RATINGS1 SYMBOL PARAMETER RATING UNIT TA Operating ambient temperature2 Note 4 °C TSTG Storage temperature –65 to +150 °C VCC All inputs with respect to GND3 –0.3 to +7 V NOTES: 1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operation sections of this specification is not implied. 2. For operating at elevated temperatures the device must be derated based on +150°C maximum junction temperature. 3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 4. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature range and operating supply range. BLOCK DIAGRAM DATA BUS BUFFER DB15– DB00 RESET MM READ/ WRITE LOGIC AND CONTROL A2–A0 BYTE R/W CE DBEN PARAMETER CONTROL SYNC/ADDRESS REGISTER 16 BITS 16 PCSAR INTERNAL BUS RECEIVER DATA/STATUS REGISTER RDSR RECEIVER LOGIC AND CONTROL 16 PARAMETER CONTROL REGISTER 8 BITS PCR VCC GND TRANSMITTER DATA/STATUS REGISTER TDSR TRANSMITTER LOGIC AND CONTROL 16 RxC RxSI TxC TxSO S/F RxE RxA RxDA RxSA TxE TxA TxBE TxU SD00058 Figure 2. Block Diagram |
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