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PMR400UN Datasheet(PDF) 2 Page - NXP Semiconductors |
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PMR400UN Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 12 page Philips Semiconductors PMR400UN N-channel µTrenchMOS™ ultra low level FET Product data Rev. 01 — 3 March 2004 2 of 12 9397 750 12665 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 4. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage (DC) 25 °C ≤ T j ≤ 150 °C - 30 V VDGR drain-gate voltage (DC) 25 °C ≤ T j ≤ 150 °C; RGS =20kΩ -30 V VGS gate-source voltage (DC) - ±8V ID drain current (DC) Tsp =25 °C; VGS = 4.5 V; Figure 2 and 3 - 0.8 A Tsp = 100 °C; VGS = 4.5 V; Figure 2 - 0.51 A IDM peak drain current Tsp =25 °C; pulsed; tp ≤ 10 µs; Figure 3 - 1.61 A Ptot total power dissipation Tsp =25 °C; Figure 1 - 0.53 W Tstg storage temperature −55 +150 °C Tj junction temperature −55 +150 °C Source-drain diode IS source (diode forward) current (DC) Tsp =25 °C - 0.44 A ISM peak source (diode forward) current Tsp =25 °C; pulsed; tp ≤ 10 µs - 0.88 A |
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