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DRV5032AJDBZT Datasheet(PDF) 4 Page - Texas Instruments |
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DRV5032AJDBZT Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 34 page  1 4 2 3 GND VCC OUT1 OUT2 Thermal Pad 1 4 2 3 GND VCC OUT NC Thermal Pad GND VCC OUT2 1 2 3 GND VCC OUT 1 2 3 4 DRV5032 SLVSDC7D – APRIL 2017 – REVISED NOVEMBER 2017 www.ti.com Product Folder Links: DRV5032 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 6 Pin Configuration and Functions FA, FB, FC, AJ, ZE Versions DBZ Package 3-Pin SOT-23 Top View FA, AJ Versions DMR Package 4-Pin X2SON Top View DU Version DBZ Package 3-Pin SOT-23 Top View DU, FD Versions DMR Package 4-Pin X2SON Top View Pin Functions PIN I/O DESCRIPTION NAME SOT-23 (FA, FB, FC, AJ, ZE) SOT-23 (DU) X2SON (FA, AJ) X2SON (DU, FD) GND 3 3 2 2 — Ground reference OUT 2 — 4 — O Omnipolar output that responds to north and south magnetic poles OUT1 — — — 4 O Unipolar output that responds to north magnetic poles near the top of the package OUT2 — 2 — 3 O Unipolar output that responds to south magnetic poles near the top of the package NC — — 3 — — No-connect. This pin is not connected to the silicon. It should be left floating or tied to ground. It should be soldered to the board for mechanical support. VCC 1 1 1 1 — 1.65-V to 5.5-V power supply. TI recommends connecting this pin to a ceramic capacitor to ground with a value of at least 0.1 µF. Thermal Pad — — PAD PAD — No-connect. This pin should be left floating or tied to ground. It should be soldered to the board for mechanical support. |
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