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SN74LVC1G132DBVR Datasheet(PDF) 1 Page - Texas Instruments |
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SN74LVC1G132DBVR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 13 page SN74LVC1G132 SINGLE 2INPUT NAND GATE WITH SCHMITT TRIGGER INPUTS SCES546A − FEBRUARY 2004 − REVISED AUGUST 2004 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Available in Texas Instruments NanoStar and NanoFree Packages D Supports 5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Max tpd of 5.3 ns at 3.3 V D Low Power Consumption, 10-µA Max ICC D ±24-mA Output Drive at 3.3 V D Ioff Supports Partial-Power-Down Mode Operation D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) description/ordering information The SN74LVC1G132 contains one 2-input NAND gate with Schmitt-trigger inputs designed for 1.65-V to 5.5-V VCC operation and performs the Boolean function Y = A • B or Y = A + B in positive logic. Because of Schmitt action, this device has different input threshold levels for positive-going (VT+) and negative-going (VT−) signals. This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING‡ NanoStar − WCSP (DSBGA) 0.23-mm Large Bump − YEP Reel of 3000 SN74LVC1G132YEPR _ _ _D5_ −40 C to 85 C NanoFree − WCSP (DSBGA) 0.23-mm Large Bump − YZP (Pb-free) Reel of 3000 SN74LVC1G132YZPR _ _ _D5_ −40 °C to 85°C SOT (SOT-23) − DBV Reel of 3000 SN74LVC1G132DBVR C3B_ SOT (SOT-23) − DBV Reel of 250 SN74LVC1G132DBVT C3B_ SOT (SC-70) − DCK Reel of 3000 SN74LVC1G132DCKR D5_ SOT (SC-70) − DCK Reel of 250 SN74LVC1G132DCKT D5_ † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Copyright 2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DBV OR DCK PACKAGE (TOP VIEW) 1 2 3 5 4 A B GND VCC Y 3 2 1 4 5 GND B A Y VCC YEP OR YZP PACKAGE (BOTTOM VIEW) NanoStar and NanoFree are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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