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LH28F800BGR-BL12 Datasheet(PDF) 11 Page - Sharp Corporation |
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LH28F800BGR-BL12 Datasheet(HTML) 11 Page - Sharp Corporation |
11 / 43 page LH28F800BG-L/BGH-L (FOR TSOP, CSP) - 11 - COMMAND BUS CYCLES NOTE FIRST BUS CYCLE SECOND BUS CYCLE REQ ’D. Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3) Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3) Read Array/Reset 1 Write X FFH Read Identifier Codes ≥ 2 4 Write X 90H Read IA ID Read Status Register 2 Write X 70H Read X SRD Clear Status Register 1 Write X 50H Block Erase 2 5 Write BA 20H Write BA D0H Word Write 2 5, 6 Write WA 40H or 10H Write WA WD Block Erase and 1 5 Write X B0H Word Write Suspend Block Erase and 1 5 Write X D0H Word Write Resume Table 3 Command Definitions (NOTE 7) NOTES : 1. Bus operations are defined in Table 2. 2. X = Any valid address within the device. IA = Identifier code address : see Fig. 2. BA = Address within the block being erased. WA = Address of memory location to be written. 3. SRD = Data read from status register. See Table 6 for a description of the status register bits. WD = Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). ID = Data read from identifier codes. 4. Following the Read Identifier Codes command, read operations access manufacture and device codes. See Section 4.2 for read identifier code data. 5. If the block is boot block, WP# must be at VIH or RP# must be at VHH to enable block erase or word write operations. Attempts to issue a block erase or word write to a boot block while WP# is VIH or RP# is VIH. 6. Either 40H or 10H is recognized by the WSM as the word write setup. 7. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. |
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