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PCM1741 Datasheet(PDF) 16 Page - Burr-Brown (TI) |
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PCM1741 Datasheet(HTML) 16 Page - Burr-Brown (TI) |
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16 / 20 page  PCM1741 16 SBAS175 ZERO FLAGS Zero Detect Condition Zero Detection for each output channel is independent from the other. If the data for a given channel remains at a “0” level for 1024 sample periods (or LRCK clock periods), a Zero Detect condition exists for that channel. Zero Output Flags Given that a Zero Detect condition exists for one or more channels, the Zero Flag pins for those channels will be set to a logic “1” state. There are Zero Flag pins for each channel: ZEROL (pin 12) and ZEROR (pin 11). These pins can be used to operate external mute circuits, or used as status indicators for a microcontroller, audio signal processor, or other digitally controlled functions. The active polarity of Zero Flag output can be inverted by setting the ZREV bit of Control Register 22 to “1”. The reset default is active high output, or ZREV = 0. The L-channel and R-channel common Zero Flag can be selected by setting the AZRO bit of Control Register 22 to “1”. The reset default is L-channel and R-channel independent Zero Flag, or AZRO = 0. APPLICATIONS INFORMATION CONNECTION DIAGRAMS A basic connection diagram is shown in Figure 11, with the necessary power-supply bypassing and decoupling compo- nents. Texas Instruments recommends using the component values shown in Figure 11 for all designs. The use of series resistors (22 Ω to 100Ω) are recommended for the SCK, LRCK, BCK, and DATA inputs. The series resistor combines with stray PCB and device input capaci- tance to form a low-pass filter that reduces high-frequency noise emissions and helps to dampen glitches and ringing present on clock and data lines. FIGURE 11. Basic Connection Diagram. 1 2 3 4 5 6 7 8 BCK DATA LRCK DGND V DD V CC V OUTL V OUTR 16 15 14 13 12 11 10 9 SCK ML MC MD ZEROL/NA ZEROR/ZEROA V COM AGND Post LPF +3.3V Regulator Mode Control Zero Mute Control System Clock PCM Audio Data Input +3.3V L-Chan OUT 10 µF 10 µF + + 10 µF Post LPF R-Chan OUT POWER SUPPLIES AND GROUNDING The PCM1741 requires a +3.3V analog supply (VCC) and a +3.3V digital supply (VDD). The +3.3V supply (VCC) is used to power the DAC analog and output filter circuitry, while the +3.3V (VDD) supply is used to power the digital filter and serial interface circuitry. For best performance, the +3.3V (VDD) supply should be derived from the +3.3V (VCC) supply using a linear regulator, as shown in Figure 11. Proper power-supply bypassing is shown in Figure 10. The 10 µF capacitors should be tantalum or aluminum electrolytic, while the 0.1 µF capacitors are ceramic (X7R type is recom- mended for surface-mount applications). FIGURE 10. Dual-Supply Filter Circuit. R 1 R 3 R 4 R 2 C 1 C 2 V IN V OUT OPA2134 2 3 1 R 2 R 1 A V ≈ – DAC OUTPUT FILTER CIRCUITS Delta-sigma DACs utilize noise-shaping techniques to im- prove in-band Signal-to-Noise Ratio (SNR) performance at the expense of generating increased out-of-band noise above the Nyquist Frequency, or fS/2. The out-of-band noise must be low-pass filtered in order to provide the optimal converter performance. This is accomplished by a combination of on-chip and external low-pass filtering. Figures 9(a) and 10 show the recommended external low- pass active filter circuits for single- and dual-supply applica- tions. These circuits are second-order Butterworth filters |
Similar Part No. - PCM1741 |
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Similar Description - PCM1741 |
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