Philips Semiconductors

Application note

AN460

Using the P82B96 for bus interface

2001 Feb 14

5

+5 V

1/2 P82B96

SU01020

SDA

Rx

Tx

1K

15 V

+5 V

1/2 P82B96

SDA

Rx

Tx

1K

15 V

LONG TWISTED PAIR

NOTE: Schottky diode and zener clamps applied to limit spurious signals

Figure 7.

Power dissipation under fault conditions

The current drive capability of the buffered Tx and Ty outputs

exceeds 100 mA. If a wiring fault causes a short from these pins to

high dissipations result when Sx or Sy are driven low. The rated 300

mW dissipation can be exceeded within a very short time.

Appropriate precautions should be taken to ensure that such a

short-circuit does not occur.

Bus characteristics and rise/fall times

In general terms, the rise times which will be observed on a bus

driven by the P82B96 will be simply determined by the pull-up

resistor used and the total capacitive load presented to the bus.

The fall time is determined mostly by the dynamic pull down current

capability and the capacitive load, with some modification caused by

the varying current in the bus pull up resistor.

The effective logic signal propagation time will depend on the input

logic thresholds of the P82B96, and of any other devices connected

On a 2 V supply, the Sx and Sy thresholds are approaching half the

supply rail. On a 5V supply their (0.65V) threshold is much closer to

GND than usual for logic inputs. This causes some additional delay

in the effective propagation time on falling edges, and reduces those

delays on the rising edges.

levels are ‘conventional’ when the buffered bus pull-ups are

the Rx threshold may need to be taken into account.

P82B96 response time for propagation of low to

high at Sx

With Tx connected to Rx, a low at Sx causes a low at Tx and thus to

Rx. The low at Rx enables a ‘clamp’ at 1V, the logic low, on Sx.

towards this 1V clamping level set by the return signal from Rx,

which is still low.

As Sx rises past its 0.65V input threshold, the Tx output drive will be

released. The Tx output voltage will begin to rise at a rate determined

by its load capacitance and the pull up resistor used at Tx.

voltage the Rx input senses that Tx has been released, and returns

a ‘high’ signal to its output at Sx, allowing this voltage to continue its

waveforms are shown in Figure 8.

This delay in termination of the low signal on Sx will be further

extended if Tx and Rx are not directly linked and there are other

delays inherent in the signal path between Tx and Rx. Including slow

opto-couplers in the loop will exaggerate these delays (see Figure 4).

Horiz: 200ns/div.

VertL 2V/div.

Sx

ch1: freq = 624 kHz

SU01071

Rx/Tx

Figure 8.

Low to High propagation of Sx with Tx linked to RX