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ISP1161A1BD Datasheet(PDF) 78 Page - NXP Semiconductors |
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ISP1161A1BD Datasheet(HTML) 78 Page - NXP Semiconductors |
78 / 136 page Philips Semiconductors ISP1161A1 USB single-chip host and device controller Product data Rev. 03 — 23 December 2004 78 of 136 9397 750 13961 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. • The SIE also checks for the device number and endpoint number and verifies whether they are acceptable. • If the endpoint is enabled, the SIE checks the contents of the DcEndpointStatus register. If the endpoint is empty, the data from USB is stored to FIFO during the data phase, otherwise a NAK handshake is sent. • After the data phase, the SIE sends a handshake (ACK) to the host (except for ISO endpoints). • The SIE updates the contents of the DcEndpointStatus register and the DcInterrupt register, which in turn generates an interrupt to the microprocessor. For ISO endpoints, the DcInterrupt register is updated as soon as data is received because there is no handshake phase. • On receiving interrupt, the microprocessor reads the DcInterrupt register. It will know which endpoint has generated the interrupt and reads the content of the corresponding DcEndpointStatus register. If the buffer is full, it empties the buffer, so that data can be received by the SIE at the next OUT token phase. 11.2 Device DMA transfer 11.2.1 DMA for IN endpoint (internal DC to external USB host) When the internal DMA handler is enabled and at least one buffer (Ping or Pong) is free, the DREQ2 line is asserted. The external DMA controller then starts negotiating for control of the bus. As soon as it has access, it asserts the DACK2 line and starts writing data. The burst length is programmable. When the number of bytes equal to the burst length has been written, the DREQ2 line is de-asserted. As a result, the DMA controller de-asserts the DACK2 line and releases the bus. At that moment the whole cycle restarts for the next burst. When the buffer is full, the DREQ2 line will be de-asserted and the buffer is validated (which means that it will be sent to the host when the next IN token comes in). When the DMA transfer is terminated, the buffer is also validated (even if it is not full). A DMA transfer is terminated when any of the following conditions are met: • the DMA count is complete • bit DMAEN = 0 • the DMA controller asserts EOT. 11.2.2 DMA for OUT endpoint (external USB host to internal DC) When the internal DMA handler is enabled and at least one buffer is full, the DREQ2 line is asserted. The external DMA controller then starts negotiating for control of the bus, and as soon as it has access, it asserts the DACK2 line and starts reading the data. The burst length is programmable. When the number of bytes equal to the burst length has been read, the DREQ2 line is de-asserted. As a result, the DMA controller de-asserts the DACK2 line and releases the bus. At that moment the whole cycle restarts for the next burst. When all data are read, the DREQ2 line will be de-asserted and the buffer is cleared (which means that it can be overwritten when a new packet comes in). |
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