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IRU3046 Datasheet(PDF) 8 Page - International Rectifier |
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IRU3046 Datasheet(HTML) 8 Page - International Rectifier |
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8 / 20 page  8 Rev. 1.9 09/27/02 IRU3046 www.irf.com The RDS(ON) temperature dependency should be consid- ered for the worst case operation. This is typically given in the MOSFET data sheet. Ensure that the conduction losses and switching losses do not exceed the package ratings or violate the overall thermal budget. Choose IRF7460 for control MOSFET and IRF7457 for synchronous MOSFET. These devices provide low on- resistance in a compact SOIC 8-Pin package. The MOSFETs have the following data: The total conduction losses for the master channel is: The total conduction losses for the slave channel is: The control MOSFET contributes to the majority of the switching losses in synchronous Buck converter. The synchronous MOSFET turns on under zero-voltage con- dition, therefore the turn on losses for synchronous MOSFET can be neglected. With a linear approxima- tion, the total switching loss can be expressed as: Figure 4 - Switching time waveforms. From IRF7460 data sheet we obtain: These values are taken under a certain condition test. For more detail please refer to the IRF7460 and IRF7457 data sheets. By using equation (7), we can calculate the switching losses. Feedback Compensation The control scheme for master and slave channels is based on voltage mode control, but the compensation of these two feedback loops is slightly different. The Master channel sets the output voltage and its feed- back loop should take care of double pole introduced by the output filter as a regular voltage mode control loop. The goal is to provide a close loop transfer function with the highest 0dB crossing frequency and adequate phase margin. The slave feedback loop acts slightly different and its goal is using the current information for current sharing. The master feedback loop sees the output filter. The out- put LC filter introduces a double pole, -40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180 8 (see Figure 5). The resonant frequency of the LC filter expressed as follows: Figure 5 shows gain and phase of the LC filter. Since we already have 180 8 phase shift just from the output filter, the system risks being unstable. Figure 5 - Gain and phase of LC filter. PSW(MASTER) = 44.8mW PSW(SLAVE) = 107.5mW PCON(MASTER) = 0.85W PCON(SLAVE) = 0.77W IRF7460 VDSS = 20V ID = 10A @ 75 8C RDS(ON) = 10m V @ VGS=10V q = 1.8 for 1508C (Junction Temperature) IRF7457 VDSS = 20V ID = 12A @ 70 8C RDS(ON) = 7.5m V @ VGS=10V q = 1.5 for 1508C (Junction Temperature) Where: VDS(OFF) = Drain to Source Voltage at off time tr = Rise Time tf = Fall Time T = Switching Period ILOAD = Load Current PSW = 3 3 ILOAD ---(7) VDS(OFF) 2 tr + tf T FLC(MASTER) = ---(8) 1 2 p Lo 3Co IRF7460 tr = 6.9ns tf = 4.3ns VDS VGS 10% 90% td(ON) td(OFF) tr tf Gain FLC 0dB Phase 0 8 FLC -180 8 Frequency Frequency -40dB/decade |
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