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IDT85304-01 Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT85304-01 Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 11 page 2 COMMERCIALANDINDUSTRIALTEMPERATURERANGES IDT85304-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PIN CONFIGURATION NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute- maximum-rated conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max Unit VDD Power Supply Voltage 4.6 V VI Input Voltage –0.5 to VDD+0.5 V VO Output Voltage –0.5 to VDD+0.5 V θJA PackageThermalImpedance(0lfpm) 92.6 °C/W TSTG Storage Temperature –65 to +150 °C CAPACITANCE(TA=+25°C,f=1MHz,VIN=0V) Parameter Description Typ. Max. Unit CIN InputCapacitance — 4 pF RPULLUP InputPullupResistor 51 — K Ω RPULLDOWN InputPulldownResistor 51 — K Ω TSSOP TOP VIEW 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 xQ0 Q1 xQ1 Q2 xQ2 Q3 xQ3 Q4 xQ4 VDD CLK_EN VDD xPCLK PCLK VEE xCLK CLK CLK_SEL VDD PIN DESCRIPTION(1) Symbol Number Type Description xQ0, Q0 1, 2 Output DifferentialOutputPair. LVPECLinterfacelevels. xQ1, Q1 3, 4 Output DifferentialOutputPair. LVPECLinterfacelevels. xQ2, Q2 5, 6 Output DifferentialOutputPair. LVPECLinterfacelevels. xQ3, Q3 7, 8 Output DifferentialOutputPair. LVPECLinterfacelevels. xQ4, Q4 9, 10 Output DifferentialOutputPair. LVPECLinterfacelevels. VDD 11, 18, 20 Power Positive Supply Pins CLK_SEL 12 Input Pulldown ClockSelectInput. WhenHIGH,selectsPCLK/xPCLKinputs. WhenLOW,selects CLK / xCLK inputs. LVTTL / LVCMOS interface levels. CLK 13 Input Pulldown Non-InvertingDifferentialClockInput xCLK 14 Input Pullup InvertingDifferentialClockInput VEE 15 Power Negative Supply Pin PCLK 16 Input Pulldown Non-InvertingDifferentialLVPECLClockInput xPCLK 17 Input Pullup InvertingDifferentialLVPECLClockInput CLK_EN 19 Input Pullup SynchronizingClockEnable. WhenHIGH,clockoutputsfollowclockinput. When LOW, Q outputs are forced LOW, xQ outputs are forced HIGH. LVTTL / LVCMOS interfacelevels. NOTE: 1. Pullup and Pulldown refer to internal input resistors. See Capacitance table for typical values. |
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