DS_K6F1016U4C datasheet(8/9 Pages) SAMSUNG

Part #	DS_K6F1016U4C

Description	64K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM

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Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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8 / 9 page

Revision 2.0

CMOS SRAM

September 2003

K6F1016U4C Family

- 8 -

Address

CS

Data Valid

UB, LB

WE

Data in

Data out

High-Z

TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-

tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS going low to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

tWC

tCW(2)

tBW

tWP(1)

tDH

tDW

tWR(4)

tAW

DATA RETENTION WAVE FORM

VCC

2.7V

2.2V

VDR

CS, LB/UB

GND

tAS(3)

Data Retention Mode

CS

≥VCC - 0.2V or LB=UB≥Vcc-0.2V

tSDR

tRDR

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DS_K6F1016U4C Datasheet(PDF) 8 Page - Samsung semiconductor

DS_K6F1016U4C Datasheet(HTML) 8 Page - Samsung semiconductor

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