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CY28339
Document #: 38-07507 Rev. *A
Page 8 of 18
PD# Deassertion
The power-up latency between PD# rising to a valid logic ‘1’
level and the starting of all clocks is less than 3.0 ms.
CPU_STOP# Clarification
The CPU_STOP# signal is an active LOW input used to
synchronously stop and start the CPU output clocks while the
rest of the clock generator continues to function.
CPU_STOP# Assertion
When CPU_STOP# pin is asserted, all CPUT/C outputs that
are set with the SMBus configuration to be stoppable via
assertion of CPU_STOP# will be stopped after being sampled
by two falling CPUT/C clock edges. The final state of the
stopped CPU signals is CPUT = HIGH and CPU0C = LOW.
There is no change to the output drive current values during
the stopped state. The CPUT is driven HIGH with a current
value equal to (Mult 0 “select”) × (Iref), and the CPUC signal
will not be driven. Due to external pull-down circuitry CPUC will
be LOW during this stopped state.
CPU 133MHz
3V66
CPU# 133MHz
REF 14.318MHz
USB 48MHz
PCIF / APIC
33MHz
66In
66Buff
PW RDW N#
66Buff1 / GMCH
400uS max
<1.8mS
PCI 33MHz
30uS min
Figure 4. Power-down Deassertion Timing Waveforms – Buffered Mode
CPU_STP#
CPUT
CPUC
CPUT
CPUC
Figure 5. CPU_STOP# Assertion Waveform
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