11 / 33 page  CY7C1371C CY7C1373C Document #: 38-05234 Rev. *D Page 11 of 33 TDI - U3 P5 JTAG serial input Synchronous Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available on TQFP packages. TMS - U2 R5 JTAG serial input Synchronous Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TCK - U4 R7 JTAG-Clock Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. NC 1,2,3,6,7,16, 25,28,29,30, 38,39,42,43, 51,52,53,56, 57,66,75,78, 79,95,96,14 B1,B7,C1, C7,D2,D4, D7,E1,E6, H2,F2,G1, G6, H7,J3,J5, K1,K6,L4, L2,L7,M6, N2,N7,L7, P1,P6,R1, R5,R7,T1, T4,U6 A1,A5,B1, B4,B11, C1,C2,C10, D1,D10,E1, E10,F1,F10, G1,G10,H1, H3,H9,H10, J2,J11,K2, K11,L2,L11, M2,M11,N2, N5,N6,N7, N10,N11,P1, P2,P11,R2 - No Connects. Not internally connected to the die. 18M,36M, 72M, 144M and 288M are address expansion pins and are not internally connected to the die. NC / VDD –– H2 – Can either be left unconnected or connected to VDD. Must not be connected to VSS. CY7C1373C–Pin Definitions (continued) Name TQFP BGA fBGA I/O Description |
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