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CY7C0850V/CY7C0851V
CY7C0852V/CY7C0853V
Document #: 38-06070 Rev. *D
Page 2 of 29
Note:
1.
, 9M device has 18 address bits, 4M device has 17 address bits, 2M device has 16 address bits, and 1M device has 15 address bits.
Logic Block Diagram[1]
A0L–A17L
CLKL
ADSL
CNTENL
CNTRSTL
True
RAM Array
18
Addr.
Read
Back
CNTINTL
Mask Register
Counter/
Address
Register
CNT/MSKL
Address
Decode
Dual-Ported
Interrupt
Logic
INTL
Reset
Logic
JTAG
TDO
TMS
TCK
TDI
MRST
DQ9L–DQ17L
DQ0L–DQ8L
I/O
Control
9
9
9
9
DQ18L–DQ26L
DQ27L–DQ35L
CE0L
CE1L
R/WL
B0L
B1L
B2L
B3L
OEL
A0R–A17R
CLKR
ADS
CNTEN
CNTRSTR
18
Addr.
Read
Back
CNTINTR
Mask Register
Counter/
Address
Register
CNT/MSKR
Address
Decode
Interrupt
Logic
INTR
DQ9R–DQ17R
DQ0R–DQ8R
I/O
Control
9
9
9
9
DQ18R–DQ26R
DQ27R–DQ35R
CE0R
CE1R
R/WR
B0R
B1R
B2R
B3R
OER
Mirror Reg
Mirror Reg