AT40K10LV-3RQC datasheet(11/67 Pages) ATMEL

Part #	AT40K10LV-3RQC

Description	5K - 50K Gates Coprocessor FPGA with FreeRAM

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Manufacturer	ATMEL [ATMEL Corporation]

Direct Link	http://www.atmel.com

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AT40K/AT40KLV Series FPGA

0896C–FPGA–04/02

RAM

32 x 4 dual-ported RAM blocks are dispersed throughout the array, see Figure 7. A 4-bit

Input Data Bus connects to four horizontal local buses distributed over four sector rows

(plane 1). A 4-bit Output Data Bus connects to four horizontal local buses distributed

over four sectors in the same column. A 5-bit Output Address Bus connects to five verti-

cal express buses in the same column. Ain (input address) and Aout (output address)

alternate positions in horizontally aligned RAM blocks. For the left-most RAM blocks,

Aout is on the left and Ain is on the right. For the right-most RAM blocks, Ain is on the

left and Aout is tied off, thus it can only be configured as a single port. For single-ported

RAM, Ain is the READ/WRITE address port and Din is the (bi-directional) data port.

Right-most RAM blocks can be used only for single-ported memories. WEN and OEN

connect to the vertical express buses in the same column.

Figure 7. RAM Connections (One Ram Block)

32 x 4 RAM

CLK

Din

Ain

WEN

OEN

Dout

Aout

CLK

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