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AD9250BCPZ-170 Datasheet(PDF) 10 Page - Analog Devices |
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AD9250BCPZ-170 Datasheet(HTML) 10 Page - Analog Devices |
10 / 45 page AD9250 Data Sheet Rev. E | Page 10 of 45 TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit SPI TIMING REQUIREMENTS (See Figure 62) tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CS and SCLK 2 ns tH Hold time between CS and SCLK 2 ns tHIGH Minimum period that SCLK should be in a logic high state 10 ns tLOW Minimum period that SCLK should be in a logic low state 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in figures) 10 ns tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in figures) 10 ns tSPI_RST Time required after hard or soft reset until SPI access is available (not shown in figures) 500 µs Timing Diagrams N – 36 N – 35 N – 34 N – 33 N – 1 N + 1 SAMPLE N ANALOG INPUT SIGNAL CLK– CLK+ CLK– CLK+ SERDOUT1± SERDOUT0± SAMPLE N – 36 ENCODED INTO 2 8b/10b SYMBOLS SAMPLE N – 35 ENCODED INTO 2 8b/10b SYMBOLS SAMPLE N – 34 ENCODED INTO 2 8b/10b SYMBOLS Figure 2. Data Output Timing tREFS tREFH tREFHRF NOTES 1. CLOCK INPUT IS EITHER RFCLK OR CLK±, NOT BOTH. CLK+ CLK– SYSREF+ SYSREF– RFCLK SYSREF+ SYSREF– tREFSRF Figure 3. SYSREF± Setup and Hold Timing |
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