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AD9250 Datasheet(PDF) 3 Page - Analog Devices

Part # AD9250
Description  Dual Analog-to-Digital Converter
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9250 Datasheet(HTML) 3 Page - Analog Devices

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Data Sheet
AD9250
Rev. E | Page 3 of 45
REVISION HISTORY
9/2017—Rev. D to Rev. E
Changes to Channel-Specific Registers Section................................. 36
Changes to Table 18................................................................................... 37
Changes to Figure 63 and Table 19........................................................ 43
5/2017—Rev. C to Rev. D
Change to Differential Output Voltage (VOD) Parameter, Table 3....8
Deleted Synchronization Section..................................................26
Changes to Link Setup Parameters Section .................................26
Deleted Clock Adjustment Register Writes Section ...................27
Added Internal FIFO Timing Optimization Section .................28
Changes to Table 14 ........................................................................30
Changes to Channel-Specific Registers Section..........................36
Deleted Transfer Register Map Section........................................37
Changes to Table 18 ........................................................................37
Added SPI Initialization Sequence Section..................................42
Added Figure 63 and Table 19; Renumbered Sequentially........43
Deleted JESD204B Configuration Section...................................44
Updated Outline Dimensions........................................................45
1/2016—Rev. B to Rev. C
Moved Revision History Section.....................................................3
Changes to Nyquist Clock Input Options....................................22
Added Synchronization Section....................................................26
Added Click Adjustment Register Writes Section ......................27
Changes to Link Setup Parameters Section .................................27
Change to Additional Digital Output Configuration Options
Section ..............................................................................................29
Added Table 14, Renumbered Sequentially.................................30
Changes to Table 18 ........................................................................38
Added JESD204B Configuration Section ....................................43
12/2013—Rev. A to Rev. B
Change to Features Section..............................................................1
Change to Functional Block Diagram............................................1
Change to SYNCIN Input (SYNCINB+/SYNCINB−), Logic
Compliance Parameter, Table 3.......................................................6
Changes to Data Output Parameters, Table 4 ...............................8
Changes to Figure 3 ..........................................................................9
Change to Figure 30, Added Figure 34 through Figure 37;
Renumbered Sequentially ..............................................................17
Changes to Table 9 ..........................................................................20
Change to Figure 47........................................................................21
Changes to JESD204B Overview Section ....................................24
Change to Configure Details Options Section............................26
Change to Check FCHK, Checksum of JESD204B Interface
Parameters Section..........................................................................27
Changes to Figure 54 ......................................................................28
Changes to Figure 57 and Figure 58 .............................................29
Changes to Figure 59 and Figure 60 .............................................30
Changes to Table 17 ........................................................................36
Updated Outline Dimensions........................................................42
3/2013—Rev. 0 to Rev. A
Changes to High Level Input Current and Low Level Input
Current; Table 3.................................................................................6
Changes to Table 4 ............................................................................8
Changes to Figure 3 Caption ...........................................................9
Changes to Digital Inputs Description; Table 8 ..........................11
Changes to JESD204B Synchronization Details Section ...........24
Changes to Configure Detailed Options Section........................25
Changes to Fast Threshold Detection (FDA and FDB) Section ...30
Deleted Built-In Self-Test (BIST) and Output Test Section ......32
Changes to Transfer Register Map Section..................................34
Changes to Table 17 ........................................................................35
10/2012—Revision 0: Initial Version


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