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PC107AVZFU100LD Datasheet(PDF) 2 Page - ATMEL Corporation |
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PC107AVZFU100LD Datasheet(HTML) 2 Page - ATMEL Corporation |
2 / 50 page 2 PC107A [Preliminary] 2137C–HIREL–03/04 General Description Simplified Block Diagram The PC107A integrates a PCI bridge, memory controller, DMA controller, EPIC interrupt controller/timers, a message unit with an Intelligent Input/Output (I 2O) message control- ler, and an Inter-integrated Circuit (two-wire interface) controller. The integration reduces the overall packaging requirements and the number of discrete devices required for an embedded system. Figure 1 shows the major functional units within the PC107A. Note that this is a concep- tual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented. Figure 1. PC107A Block Diagram Data (64-Bit) 60x Bus Interface (64- or 32-Bit Data Bus) Address (32-Bit) DLL PLL Fanout Buffers Additional features: • Programmable I/O • with Watchpoint • JTAG/COP Interface • Power Management SDRAM_SYNC_IN SDRAM Clocks CPU Clocks PCI_SYNC_IN PCI Bus Clocks Memory/ROM/ Port X Control/ Address Data Bus (64- or 32-bit) with 8-bit Parity or ECC OSC_IN Five Request/Grant Pairs 32-Bit PCI Interface I2C 5 IRQs/ 16 Serial Interrupts EPIC Interrupt Controller /Timers Address Translator PCI Arbiter MPC107 I2C Controller DMA Controller Message Unit (with I2O) Peripheral Logic Block Central Control Unit Data Path ECC Controller Memory Controller Configuration Registers PCI Bus Interface Unit |
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