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AD9625BBPRL-2.6 Datasheet(PDF) 38 Page - Analog Devices |
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AD9625BBPRL-2.6 Datasheet(HTML) 38 Page - Analog Devices |
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38 / 74 page  AD9625 Data Sheet Rev. C | Page 36 of 72 LOW BANDWIDTH DECIMATOR Use the second filter stage in the optional low bandwidth mode only. It achieves an additional rate reduction factor of 2, yielding a final sample rate of 2.500 GHz/16 = 156.25 MHz. The internal architecture of the low bandwidth decimation filter is similar to that of a high bandwidth decimator. Moreover, for ease of physical design, the block operates at 312.5 MHz, a result of which both the I- and Q-phases can share the filter engine. The performance of the low bandwidth decimation filter is shown in Figure 85 and Figure 86. The filter yields an effective bandwidth of 60 MHz, with a transition band of 81.25 MHz − 60 MHz = 21.25 MHz. Thus, the two sided, complex bandwidth of the filter is 120 MHz. A rejection ratio of 85 dB ensures that the alias region folds back well below the noise floor of the input signal. As with the high bandwidth filter, this block provides user specified gain control, from 0 dB to 18 dB, in steps of 6 dB. The gain is applied before final quantization at the output of the low bandwidth decimation filter to 16 bits. 10 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 0 160 140 120 100 80 60 40 20 FREQUENCY (MHz) Figure 85. Magnitude Response of Decimate-by-2 Filter –0.2 –0.1 0 0.1 0.2 0.3 0.4 060 50 40 30 20 10 FREQUENCY (MHz) Figure 86. Magnitude Ripple in the Low Bandwidth Pass Band The low bandwidth decimator has a filter architecture that consists of a 31 tap delay line. The coefficients are 17 bits each and are listed in Table 13. Table 13. Filter Tap Coefficients for Low Bandwidth Decimator Tap Number Coefficient 1 +126 2 +312 3 −16 4 −859 5 −628 6 +1217 7 +1428 8 −1944 9 −3227 10 +2511 11 +6302 12 −3099 13 −13075 14 +3441 15 +43442 16 +65536 17 +43442 18 +3441 19 −13075 20 −3099 21 +6302 22 +2511 23 −3227 24 −1944 25 +1428 26 +1217 27 −628 28 −859 29 −16 30 +312 31 +126 |
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