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AD9625BBPRL-2.5 Datasheet(PDF) 70 Page - Analog Devices

Part No. AD9625BBPRL-2.5
Description  1.3 V/2.5 V Analog-to-Digital Converter
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9625BBPRL-2.5 Datasheet(HTML) 70 Page - Analog Devices

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AD9625
Data Sheet
Rev. C | Page 68 of 72
Table 101. Interrupt Request (IRQ) Mask Control Register, Address 0x101 (Default = 0xBC)
Bit No.
Access
Bit Description
7
RW
Interrupt request PLL lock error masked.
1: PLL unlocked events are masked.
6
Unused.
5
RW
Must be set to 1.
4
RW
Must be set to 1.
3
RW
Interrupt request SYSREF± hold error.
1: a hold error has occurred with the last SYSREF± signal received. To clear this error, set and clear Bit 6 in Register 0x03A.
2
RW
Interrupt request SYSREF± setup error.
1: a setup error has occurred with the last SYSREF± signal received. To clear this error, set and clear Bit 6 in Register 0x03A.
1
Unused.
0
RW
Interrupt request clock error mask.
1: clock error has occurred and the validity of the output data cannot be guaranteed. The only way to recover from this
error is to reset the device.
Table 102. Digital Control Register, Address 0x105 (Default = 0x00)
Bit No.
Access
Bit Description
[7:5]
Unused.
4
RW
Must be set to 0.
3
RW
Must be set to 0.
2
RW
Must be set to 0.
1
RW
Must be set to 0.
0
RW
Must be set to 0.
Table 103. Digital Calibration Threshold Control Register, Address 0x10A (Default = 0x10)
Bit No.
Access
Bit Description
[7:5]
Unused.
4
RW
Enable data set threshold logic for background gain.
[0:3]
Unused.
Table 104. Digital Calibration Data Set Threshold Register, Address 0x10D (Default = 0x3D)
Bit No.
Access
Bit Description
[7:0]
RW
Data set threshold for background gain calibration.
Table 105. Digital Calibration Data Set Threshold Register, Address 0x10E (Default = 0x14)
Bit No.
Access
Bit Description
[7:0]
RW
Data set threshold for background gain calibration.
Table 106. DIVCLK± Output Control Register, Address 0x120 (Default = 0x11)
Bit No.
Access
Bit Description
[7:5]
Unused.
4
RW
DIVCLK± output disable. DIVCLK± is 1/4th of the sample clock frequency.
0: DIVCLK± output is disabled.
1: DIVCLK± output is enabled.
3
RW
DIVCLK± output termination selection.
0: DIVCLK± output uses an external 100 Ω resistive termination.
1: DIVCLK± output uses no external resistive termination.
2
Unused.
[1:0]
RW
Control the differential swing for the DIVCLK± output.
00: 100 mV p-p differential.
01: 200 mV p-p differential.
10: 300 mV p-p differential.
11: 400 mV p-p differential.


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