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AD9625BBPRL-2.5 Datasheet(PDF) 61 Page - Analog Devices |
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AD9625BBPRL-2.5 Datasheet(HTML) 61 Page - Analog Devices |
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61 / 74 page  Data Sheet AD9625 Rev. C | Page 59 of 72 Table 54. JESD204B Link Control Register 1, Address 0x05F (Default = 0x14) Bit No. Access Bit Description 7 Unused. 6 RW JESD204B serial tail bit, PN, enable. Note that the following equation can be used to determine the number of PN bits sent per sample = N' − N – CS (the number of control bits per sample). 0: serial tail bit, PN, disabled. Unused extra tail bits are padded with zeros. 1: serial tail bit, PN, enabled. Unused extra tail bits are padded with a pseudo random number sequence from a 31-bit LFSR (see JESD204B 5.1.4). 5 RW JESD204B serial test sample enable. 0: JESD204B test samples disabled. 1: JESD204B test samples enabled. The transport layer test sample sequence (as specified in JESD204B Section 5.1.6.2) is sent on all link lanes. 4 RW JESD204B serial lane synchronization enable. Note that the frame character insertion must be enabled (Register 0x05F[1] = 0) to enable lane synchronization. 0: lane synchronization disabled. Both sides do not perform lane synchronization; frame alignment character insertion always uses /K28.7/ control characters (see JESD204B 5.3.3.4). 1: lane synchronization enabled. Both sides perform lane sync; frame alignment character insertion uses either /K28.3/ or /K28.7/ control characters (see JESD204B 5.3.3.4). [3:2] RW JESD204B serial initial lane alignment sequence mode. 00: initial lane alignment sequence disabled (JESD204B 5.3.3.5). 01: initial lane alignment sequence enabled (JESD204B 5.3.3.5). 10: reserved. 11: initial lane alignment sequence always on test mode; the JESD204B data link layer test mode (where repeated lane alignment sequence, as specified in JESD204B section 5.3.3.9.2) is sent on all lanes. 1 RW JESD204B serial frame alignment character insertion (FACI) disable. 0: frame alignment character insertion enabled (JESD204B 5.3.3.4). 1: frame alignment character insertion disabled. Note that this is for debug only (JESD204B 5.3.3.4). 0 RW JESD204B serial transmit link power-down (active high). Note that the JESD204B transmitter link must be powered down while changing any of the link configuration bits. 0: JESD204B serial transmit link enabled. Transmission of the /K28.5/ characters for code group synchronization is controlled by the SYNCINB± pins. 1: JESD204B serial transmit link powered down (held in reset and clock gated). Table 55. JESD204B Link Control Register 2, Address 0x060 (Default = 0x00) Bit No. Access Bit Description [7:6] RW JESD204B serial synchronization mode. 00: normal mode. 01: reserved. 10: SYNCINB± active mode. SYNCINB± pins are active: force code group synchronization. 11: SYNCINB± pins disabled. 5 RW JESD204B serial synchronization pin invert. 0: SYNCINB± pins not inverted. 1: SYNCINB± pins inverted. [4:3] Unused. 2 RW JESD204B Serial 8-bit/10-bit bypass (test mode only). 0: 8-bit/10-bit enabled. 1: 8-bit/10-bit bypassed (most significant two bits are 0). 1 RW JESD204B 10-bit serial transmit bit invert. Note that in the event that the CML signals are reversed in a system board layout, this bit effectively inverts the differential outputs from the PHY. 0: normal. 1: invert the a, b, c, d, e, f, g, h, i, j bits. 0 RW JESD204B 10-bit serial transmit bit mirror. 0: 10-bit serial bits are not mirrored. Transmit bit order is alphabetical: a, b, c, d, e, f, g, h, i, j. 1: 10-bit serial bits are mirrored. Transmit bit order is alphabetically reversed: j, i, h, g, f, e, d, c, b, a. |
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