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AD9625BBPRL-2.5 Datasheet(PDF) 60 Page - Analog Devices

Part No. AD9625BBPRL-2.5
Description  1.3 V/2.5 V Analog-to-Digital Converter
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9625BBPRL-2.5 Datasheet(HTML) 60 Page - Analog Devices

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AD9625
Data Sheet
Rev. C | Page 58 of 72
Table 52. Fast Detect Dwell Time Counter Threshold Register, Address 0x04C (Default = 0x00)
Bit No.
Access
Bit Description
[7:0]
RW
These bits are the MSBs of the fast detect dwell time counter target. This is the value for a 16-bit counter that
determines the length of time that the ADC data must remain below the lower threshold before the FD pin resets to 0.
Note that the fast detect (FD) pin deasserts after the ADC codes stay below the lower target for the number of samples
indicated by the value in Register 0x04C[7:0].
Table 53. JESD204B Quick Configuration Register, Address 0x05E (Default = 0x00)
Bit No.
Access
Bit Description
[7:0]
RW
JESD204B serial quick configuration (self clearing). This register is self clearing and does not control anything in the
AD9625 directly; it only changes the value of the other JESD240B registers that control the chip. Because this register is
self clearing, it always returns to 000 after each write. To use the quick configuration feature, write to this register first,
then, if there are any changes that need to be made to any of the following settings, write to the other JESD204B
registers.
0x00: configuration determined by other registers. Because the register is self clearing, it always returns to this value
after each write.
0x01: reserved.
0x02: Generic Two Lane Configuration Register 0x063[3:0] = 0x0; Register 0x06E[4:0] = 0x1; Register 0x072[4:0] = 0xB;
Register 0x073[4:0] = 0xF.
0x04: Generic Four Lane Configuration Register 0x063[3:0] = 0x0; Register 0x06E[4:0] = 0x3; Register 0x072[4:0] = 0xB;
Register 0x073[4:0] = 0xF.
0x06: Generic Six Lane Configuration Register 0x063[3:0] = 0x0; Register 0x06E[4:0] = 0x5; Register 0x072[4:0] = 0xB;
Register 0x073[4:0] = 0xB.
0x08: Generic Eight Lane Configuration Register 0x063[3:0] = 0x0; Register 0x06E[4:0] = 0x7; Register 0x072[4:0] = 0xB;
Register 0x073[4:0] = 0xF.
0x42: reserved.
0x44: reserved.
0x48: fS × 2 mode, eight lanes. Register 0x063[3:0] = 0x4; Register 0x06E[4:0] = 0x7; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0x81: 1 DDC (high BW), one lane. Register 0x063[3:0] = 0x8; Register 0x06E[4:0] = 0x0; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0x82: 1 DDC (high BW), two lanes. Register 0x063[3:0] = 0x8; Register 0x06E[4:0] = 0x1; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0x91: 1 DDC (low BW), one lane. Register 0x063[3:0] = 0x9; Register 0x06E[4:0] = 0x0; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0xC1: 2 DDCs (high BW), one lane. Register 0x063[3:0] = 0xC; Register 0x06E[4:0] = 0x0; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0xC2: 2 DDCs (high BW), two lanes. Register 0x063[3:0] = 0xC; Register 0x06E[4:0] = 0x1; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0xC4: 2 DDCs (high BW), four lanes. Register 0x063[3:0] = 0xC; Register 0x06E[4:0] = 0x3; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0xD1: 2 DDCs (low BW), one lane. Register 0x063[3:0] = 0xD; Register 0x06E[4:0] = 0x0; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0xD2: 2 DDCs (low BW), two lanes. Register 0x063[3:0] = 0xD; Register 0x06E[4:0] = 0x1; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0xE1: 2 DDCs (mixed BW), one lane. Register 0x063[3:0] = 0xE; Register 0x06E[4:0] = 0x0; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0xE2: 2 DDCs (mixed BW), two lanes. Register 0x063[3:0] = 0xE; Register 0x06E[4:0] = 0x1; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0xE4: 2 DDCs (mixed BW), four lanes. Register 0x063[3:0] = 0xE; Register 0x06E[4:0] = 0x3; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
All other values have no effect.


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