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AD9625BBPRL-2.5 Datasheet(PDF) 59 Page - Analog Devices

Part No. AD9625BBPRL-2.5
Description  1.3 V/2.5 V Analog-to-Digital Converter
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9625BBPRL-2.5 Datasheet(HTML) 59 Page - Analog Devices

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Data Sheet
AD9625
Rev. C | Page 57 of 72
Bit No.
Access
Bit Description
4
RW
SYSREF± transition selection.
0: SYSREF± is valid on low to high transitions using selected CLK edge.
1: SYSREF± is valid on high to low transitions using selected CLK edge.
3
RW
SYSREF± capture edge selection.
0: captured on rising edge of CLK input.
1: captured on falling edge of CLK input.
2
RW
SYSREF± next mode.
0: continuous mode.
1: next SYSREF± mode: uses the next valid edge only of the SYSREF± pin. Subsequent edges of the SYSREF± pin are
ignored. When the next system reference is found, Bit 1 of Register 0x03A clears.
1
RW
SYSREF± pins enable.
0: SYSREF± disabled.
1: SYSREF± enabled. When Register 0x03A, Bit 2 = 1, only the next valid edge of the SYSREF± pins is used. Subsequent
edges of the SYSREF± pin are ignored.
0
Unused.
Table 46. Fast Detect Control Register, Address 0x045 (Default = 0x00)
Bit No.
Access
Bit Description
[7:4]
Unused.
3
RW
Force the fast detect output pin.
0: normal operation of fast detect pin.
1: force a value on the fast detect pin (see Bit 2 in this table, Table 46).
2
RW
The fast detect output pin is set to the value in this bit (Register 0x045[2]) when the output is forced.
1
Unused.
0
RW
Enable fast detect on the corrected ADC data.
0: fine fast detect disabled.
1: fine fast detect enabled.
Table 47. Fast Detect Upper Threshold Register, Address 0x047 (Default = 0x00)
Bit No.
Access
Bit Description
[7:0]
RW
These bits are the LSBs of the fast detect upper threshold. These eight LSBs of the programmable 12-bit upper threshold
are compared to the fine ADC magnitude.
Table 48. Fast Detect Upper Threshold Register, Address 0x048 (Default = 0x00)
Bit No.
Access
Bit Description
[7:4]
Unused.
[3:0]
RW
These bits are the MSBs of the fast detect upper threshold. These four MSBs of the programmable 12-bit upper
threshold are compared to the fine ADC magnitude.
Table 49. Fast Detect Lower Threshold Register, Address 0x049 (Default = 0x00)
Bit No.
Access
Bit Description
[7:0]
RW
These bits are the LSBs of the fast detect lower threshold. These eight LSBs of the programmable 12-bit lower threshold
are compared to the fine ADC magnitude.
Table 50. Fast Detect Lower Threshold Register, Address 0x04A (Default = 0x00)
Bit No.
Access
Bit Description
[7:4]
Unused.
[3:0]
RW
MSBs of the fast detect lower threshold. These four MSBs of the programmable 12-bit lower threshold are compared to
the fine ADC magnitude.
Table 51. Fast Detect Dwell Time Counter Threshold Register, Address 0x04B (Default = 0x00)
Bit No.
Access
Bit Description
[7:0]
RW
These bits are the LSBs of the fast detect dwell time counter target. This is the value for a 16-bit counter that determines
the length of time that the ADC data must remain below the lower threshold before the FD pin reset to 0.


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