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AD9625BBPRL-2.5 Datasheet(PDF) 42 Page - Analog Devices

Part No. AD9625BBPRL-2.5
Description  1.3 V/2.5 V Analog-to-Digital Converter
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9625BBPRL-2.5 Datasheet(HTML) 42 Page - Analog Devices

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AD9625
Data Sheet
Rev. C | Page 40 of 72
Digital Outputs, Timing, and Controls
The AD9625 physical layer consists of drivers that are defined in
the JEDEC Standard No. 204B-July 2011. The differential digital
outputs are powered up by default. The drivers utilize a
dynamic 100 Ω internal termination to reduce unwanted
reflections.
Place a 100 Ω differential termination resistor at each receiver
input to result in a nominal 300 mV p-p swing at the receiver
(see Figure 89). Alternatively, single-ended 50 Ω termination
can be used. When single-ended termination is used, the termi-
nation voltage should be DRVDD/2; otherwise, 0.1 μF ac coupling
capacitors can be used to terminate to any single-ended voltage.
The AD9625 digital outputs can interface with custom ASICs
and FPGA receivers, providing superior switching performance
in noisy environments. Single point-to-point network topologies
are recommended with a single differential 100 Ω termination
resistor placed as close to the receiver inputs as possible.
OR
SERDOUT[x]+
DRVDD
VRXCM
SERDOUT[x]–
OUTPUT SWING = 300mV p-p
0.1µF
100Ω
50Ω
50Ω
0.1µF
RECEIVER
VCM = VRXCM
100Ω
DIFFERENTIAL
TRACE PAIR
Figure 89. AC-Coupled Digital Output Termination Example
If there is no far end receiver termination, or if there is poor
differential trace routing, timing errors may result. To avoid
such timing errors, it is recommended that the trace length be
less than six inches, and that the differential output traces be
close together and at equal lengths.
De-Emphasis
De-emphasis enables the receiver eye diagram mask to be met
in conditions where the interconnect insertion loss does not
meet the JESD204B specification. The de-emphasis feature
should only be used when the receiver is unable to recover the
clock due to excessive insertion loss. Under normal conditions,
it is disabled to conserve power. Additionally, enabling and
setting too high a de-emphasis value on a short link may cause
the receiver eye diagram to fail. Using the de-emphasis setting
may increase EMI. See the Memory Map section for details.
KKRD
DA
R
D
DA
R
D
DA
D
DA
R
Q
C
CD
END OF
MULTIFRAME
START OF
USER DATA
START OF LINK
CONFIGURATION
DATA
START OF
ILAS
Figure 90. Initial Lane Alignment Sequence
Table 15. AD9625 Control Characters Used in JESD204B
Abbreviation
Control Symbol
8-Bit Value
10-Bit Value
RD (Running
Disparity) = −1
10-Bit Value
RD (Running
Disparity) = +1
Description
/R/
/K28.0/
000 11100
001111 0100
110000 1011
Start of multiframe
/A/
/K28.3/
011 11100
001111 0011
110000 1100
Lane alignment
/Q/
/K28.4/
100 11100
001111 0010
110000 1101
Start of link configuration data
/K/
/K28.5/
101 11100
001111 1010
110000 0101
Group synchronization
/F/
/K28.7/
111 11100
001111 1000
110000 0111
Frame alignment


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