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AD9625BBPRL-2.5 Datasheet(PDF) 41 Page - Analog Devices

Part No. AD9625BBPRL-2.5
Description  1.3 V/2.5 V Analog-to-Digital Converter
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9625BBPRL-2.5 Datasheet(HTML) 41 Page - Analog Devices

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Data Sheet
AD9625
Rev. C | Page 39 of 72
JESD204B LINK ESTABLISHMENT
The AD9625 JESD204B Tx interface operates in Subclass 1 as
defined in the JEDEC Standard No. 204B-July 2011 specification.
It is divided into the following steps: code group synchronization,
initial lane alignment sequence, and data streaming.
Code Group Synchronization (CGS) and SYNCINB±
CGS is the process where the JESD204B receiver finds the
boundaries between the 10-bit characters in the stream of data.
During the CGS phase, the JESD204B transmit block transmits
/K28.5/ characters. The receiver (external logic device) must
locate the /K28.5/ characters in its input data stream using clock
and data recovery (CDR) techniques.
The receiver issues a synchronization request by activating the
SYNCINB± pins of the AD9625. The JESD204B Tx begins
sending /K28.5/ characters until the next LMFC boundary.
When the receiver has synchronized, it waits for the correct
reception of at least four consecutive /K28.5/ symbols. It then
deactivates SYNCINB±. The AD9625 then transmits an initial
lane alignment sequence (ILAS) on the following LMFC
boundary.
For more information on the code group synchronization
phase, refer to the JEDEC Standard No. 204B-July 2011, Section
5.3.3.1.
The SYNCINB± pin operation can be controlled by SPI. The
SYNCINB± signal is a differential LVDS mode signal by default,
but it can also be driven single ended. For more information on
configuring the SYNCINB± pin operation, refer to the Memory
Map section.
Initial Lane Alignment Sequence (ILAS)
The ILAS phase follows the CGS phase and begins on the next
LMFC boundary. The ILAS consists of four mulitframes, with
an /R/ character marking the beginning and an /A/ character
marking the end. The ILAS begins by sending an /R/ character
followed by 0 to 255 ramp data for one multiframe. On the
second multiframe, the link configuration data is sent starting
with the third character. The second character is a /Q/ character
to confirm that the link configuration data follows. All
undefined data slots are filled with ramp data. The ILAS
sequence is never scrambled.
The ILAS sequence construction is shown in Figure 90. The
four multiframes include the following:
Multiframe 1: begins with an /R/ character (K28.0) and
ends with an /A/ character (K28.3).
Multiframe 2: begins with an /R/ character followed by a
/Q/ [K28.4] character, followed by link configuration
parameters over 14 configuration octets and ends with an /A/
character. Many of the parameter values are of the notation of
the value, −1.
Multiframe 3: this is the same as Multiframe 1.
Multiframe 4: this is the same as Multiframe 1.
Data Streaming
After the initial lane alignment sequence is complete, the user
data is sent. In a usual frame, all characters are user data.
However, to monitor the frame clock and multiframe clock
synchronization, there is a mechanism for replacing characters
with /F/ or /A/ alignment characters when the data meets
certain conditions. These conditions are different for unscrambled
and scrambled data. The scrambling operation is enabled by
default but may be disabled using SPI.
For scrambled data, any 0xFC character at the end of a frame is
replaced by an /F/, and any 0x7C character at the end of a
multiframe is replaced with an /A/. The JESD204B Rx checks
for /F/ and /A/ characters in the received data stream and
verifies that they only occur in the expected locations. If an
unexpected /F/ or /A/ character is found, the receiver handles
the situation by using dynamic realignment or activating the
SYNCINB± signal for more than four frames to initiate a
resynchronization. For unscrambled data, if the final character
of two subsequent frames is equal, the second character is
replaced with an /F/ if it is at the end of a frame, and an /A/ if it
is at the end of a multiframe.
Insertion of alignment characters may be modified using SPI.
The frame alignment character insertion is enabled by default.
More information on the link controls is available in the
Memory Map section, Register 0x062.
Link Setup Parameters
The following steps demonstrate how to configure the AD9625
JESD204B interface and the output:
1.
Disable the lanes before changing configuration.
2.
Select one quick configuration option.
3.
Configure the detailed options.
4.
Check FCHK, checksum of JESD204B interface parameters.
5.
Set additional digital output configuration options.
6.
Reenable the required lane(s).
7.
Before modifying the JESD204B link parameters, disable
the link and hold it in reset.
8-Bit/10-Bit Encoder
The 8-bit/10-bit encoder converts 8-bit octets into 10-bit
characters and inserts control characters into the stream when
needed. The control characters used in JESD204B are shown in
Table 15. The 8-bit/10-bit encoding allows the signal to be dc
balanced by using the same number of ones and zeros.
The 8-bit/10-bit interface has options that may be controlled via
SPI. These operations include bypass, invert or mirror. These
options are intended to be a troubleshooting tool for the
verification of the digital front end (DFE).


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