AD9625BBPRL-2.5 datasheet(40/74 Pages) AD | 1.3 V/2.5 V Analog-to-Digital Converter

Part No.	AD9625BBPRL-2.5

Description	1.3 V/2.5 V Analog-to-Digital Converter

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Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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40 / 74 page

AD9625

Data Sheet

Rev. C | Page 38 of 72

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JESD204B INTERFACE

M = 1; L = 8; N = 12; N' = 16; CF = 0; CS = 0; CS = 0...4; K = 32; HD = 1; F = 1

400ps MIN (2.5GHz)

CLK+

(ENCODE CLOCK)

LANE A±

@ 6.25Gbps

LANE B±

@ 6.25Gbps

LANE C±

@ 6.25Gbps

LANE D±

@ 6.25Gbps

LANE E±

@ 6.25Gbps

LANE F±

@ 6.25Gbps

LANE G±

@ 6.25Gbps

LANE H±

@ 6.25Gbps

SAMPLE N + 3 [3:0],

CTTTT

SAMPLE N + 7 [3:0],

CTTTT

SAMPLE N + 11 [3:0],

CTTTT

SAMPLE N + 15 [3:0],

CTTTT

SAMPLE N + 2 [3:0],

CTTTT

SAMPLE N + 6 [3:0],

CTTTT

SAMPLE N + 10 [3:0],

CTTTT

SAMPLE N + 14 [3:0],

CTTTT

SAMPLE N + 1 [3:0],

CTTTT

SAMPLE N + 5 [3:0],

CTTTT

SAMPLE N + 9 [3:0],

CTTTT

SAMPLE N + 13 [3:0],

CTTTT

SAMPLE N [3:0],

CTTTT

SAMPLE N + 4 [3:0],

CTTTT

SAMPLE N + 8 [3:0],

CTTTT

SAMPLE N + 12 [3:0],

CTTTT

SAMPLE N + 3 [11:4]

SAMPLE N + 7 [11:4]

SAMPLE N + 11 [11:4]

SAMPLE N + 15 [11:4]

SAMPLE N + 2 [11:4]

SAMPLE N + 6 [11:4]

SAMPLE N + 10 [11:4]

SAMPLE N + 14 [11:4]

SAMPLE N + 1 [11:4]

SAMPLE N + 5 [11:4]

SAMPLE N + 9 [11:4]

SAMPLE N + 13 [11:4]

SAMPLE N [11:4]

SAMPLE N + 4 [11:4]

SAMPLE N + 8 [11:4]

SAMPLE N + 12 [11:4]

F = 1 OCTETS

Figure 88. JESD204B Lane Data Mapping

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