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AD9625BBPRL-2.5 Datasheet(PDF) 32 Page - Analog Devices |
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AD9625BBPRL-2.5 Datasheet(HTML) 32 Page - Analog Devices |
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32 / 74 page  AD9625 Data Sheet Rev. C | Page 30 of 72 ANALOG INPUT CONSIDERATIONS The AD9625 has a differential analog input, which is optimized to provide superior wideband performance and must be driven differentially. For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical. Mismatch between VIN+ and VIN− introduces undesired distortion. A wideband transformer, balun, or amplifier can provide the differential analog inputs for applications that require a single- ended to differential conversion. DIFFERENTIAL INPUT CONFIGURATIONS Optimum performance is achieved while driving the AD9625 in a differential input configuration. A passive input configura- tion can be used with a single to differential balun at the analog input to the AD9625. Because the AD9625 does not make use of an internal input buffer, an external network needs to be designed to reduce bandwidth peaking and minimize kickback from the ADC sampling capacitor. Small series resistors (R3 and R4) limit input bandwidth, but can be installed to further improve performance. Choose the input network components such that its equivalent impedance, in parallel with the 100 Ω input impedance of the AD9625, is matched to the output impedance of the balun or amplifier. Using a larger value for R3 and R4 suppresses the input kickback from the sampling capacitor seen at the input to the AD9625. However, the tradeoff is a lower usable input bandwidth and an increase in the amount of signal power needed to drive into the network for the AD9625 to sample a full-scale signal. Series isolation resistors (R5 and R6) are recommended to reduce bandwidth peaking and minimize kickback from the ADC sampling capacitor. Table 11 lists the front-end requirements. AD9625 AVDD VCM DRVDD R5 R6 R3 R4 0.1µF 0.1µF R1 R2 Figure 73. Recommended Front-End Network Table 11. Recommended Front-End Components Component Component Value R1 33 Ω to 50 Ω (termination) R2 33 Ω to 50 Ω (termination) R3 0 Ω to 33 Ω (lower for higher bandwidth) R4 0 Ω to 33 Ω (lower for higher bandwidth) R5 33 Ω R6 33 Ω AD9625 AVDD VCM DRVDD 33Ω 33Ω 0.1µF 0.1µF 50Ω 50Ω 1.5pF 0.1µF 100Ω 0.1µF ANALOG INPUT INPUT Z = 50Ω ADC INTERNAL INPUT Z Figure 74. Input Network Example for Passive Balun with High Bandwidth AD9625 25Ω 25Ω 33Ω 33Ω 0.1µF 0.1µF 33Ω 33Ω 100Ω INTERNAL 0.1µF EXTERNAL BALUN/AMP Figure 75. Input Network Example for Passive Balun and >2 GHz ADC Bandwidth AD9625 33Ω 33Ω 25Ω 25Ω 0.1µF 0.1µF 33Ω 33Ω 100Ω INTERNAL 0.1µF EXTERNAL BALUN/AMP Figure 76. Input Network Example for Passive Balun and <2 GHz ADC Bandwidth USING THE ADA4961 As an alternative to using only a passive differential balun input for wideband applications, the ADA4961 differential amplifier driver can be used (see Figure 80). The ADA4961 is a high performance BiCMOS RF differential gain amplifier (DGA) optimized for driving heavy loads out to 2.0 GHz and beyond. It typically achieves −90 dBc IMD3 performance at 500 MHz and −85 dBc at 1.5 GHz. The device also exhibits very low output noise (6.8 nV/√Hz). Together, these performance numbers result in an SFDR of 133 dB/Hz at 1.5 GHz. The ADA4961 has an internal differential input impedance of 100 Ω and a differential dynamic output impedance of 50 Ω, eliminating the need for external termination resistors. The digital adjustability provides for 1 dB resolution, thus optimizing SNR for input levels spanning 21 dB. |
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