AD9625BBPRL-2.5 datasheet(31/74 Pages) AD

Part #	AD9625BBPRL-2.5

Description	1.3 V/2.5 V Analog-to-Digital Converter

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Manufacturer	AD [Analog Devices]

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31 / 74 page

Data Sheet

AD9625

Rev. C | Page 29 of 72

TEST MODES

ADC CORE

FRAMER

SERALIZER

OUTPUT

JESD204B TEST PATTERNS

10 BIT

SPI REGISTER 0x061

BITS[5:4] = 01 AND

BITS[3:0] ≠ 0000

JESD204B

TEST PATTERNS

16 BIT

SPI REGISTER 0x061

BITS[5:4] = 00

AND BITS[3:0] ≠ 0000

JESD204B

SAMPLE

CONSTRUCTION

ADC TEST PATTERNS

12 BIT

SPI REGISTER 0x00D

BITS[3:0] ≠ 0000

TAIL

BITS

FRAME

CONSTRUCTION

8b/10b

ENCODER

SCRAMBLER

(OPTIONAL)

Figure 72. Test Modes

Table 10. Flexible Output Test Modes from SPI Register 0x00D

Output Test

Mode Bit

Sequence

Pattern Name

Digital Output Word 1

(Default Twos Complement

Format)

Digital Output Word 2 (Default Twos

Complement Format)

Subject to

Data Format

Select

0000

Off (default)

Not applicable

Yes

0001

Midscale short

0000 0000 0000

= Word 1

Yes

0010

Positive full scale

0111 1111 1111

= Word 1

Yes

0011

Negative full scale

1000 0000 0000

= Word 1

Yes

0100

Alternating checkerboard

1010 1010 1010

0101 0101 0101

No

0101

PN sequence long

Not applicable

Yes

0111

One-/zero-word toggle

1111 1111 1111

0000 0000 0000

No

1000

User test mode

User data from

Register 0x019 to

Register 0x020

User data from Register 0x019 to

Register 0x020

Yes

1111

Ramp output

N

N + 1

No

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AD9625BBPRL-2.5 Datasheet(PDF) 31 Page - Analog Devices

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