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AD9625BBPZRL-2.5 Datasheet(PDF) 50 Page - Analog Devices

Part # AD9625BBPZRL-2.5
Description  1.3 V/2.5 V Analog-to-Digital Converter
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9625BBPZRL-2.5 Datasheet(HTML) 50 Page - Analog Devices

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AD9625
Data Sheet
Rev. C | Page 48 of 72
For synchronous sampling of multiple converters using
SYSREF±, it may be possible to have a scenario shown in
Figure 102. This case uses a SYSREF± capture with the falling
edge of the encode clock first to test the SYSREF± position
using the edge detection window. The three ADC’s each receive
a SYSREF± input that may be skewed in time due to board trace
length or source variance. For ADC[0] SYSREF± meets setup/
hold to CLK±[N], ADC[1] misses setup/hold to CLK±[N], and
ADC[2] is indeterminate as it falls within the setup/hold window
and may be latched by either CLK±[N] or CLK±[N + 1].
CLK+
CLK–
SYSREF–
SYSREF+
SYSREF–
SYSREF+
SYSREF–
SYSREF+
ADC[0]
ADC[1]
ADC[2]
CLK±[N]
FALLING
CLK±[N + 1]
FALLING
CLK±[N]
RISING
?
Figure 102. SYSREF± Case From Three ADCs Having Various Phase Delays
Relative to the Falling Edge of the Encode Clock and is Latched on Different
Sample Clock Edges CLK±[N] or CLK±[N + 1]
As a solution to this case, the SYSREF± capture edge can be
changed from falling to rising, which is still captured to the
analog sample from CLK±[N]. When this is done, all three
ADC’s now meet the setup/hold time for the rising edge capture
of CLK±[N].
CLK+
CLK–
SYSREF–
SYSREF+
SYSREF–
SYSREF+
SYSREF–
SYSREF+
ADC[0]
ADC[1]
ADC[2]
CLK±[N]
FALLING
CLK±[N + 1]
FALLING
CLK±[N]
RISING
Figure 103. Changing the Latching Edge to Rising for All Three ADCs,
SYSREF± Can Now be Aligned to CLK±[N]
Test Modes
Bits[5:4] in Register 0x061 control the JESD204B interface test
injection points.
00: 16-bit test generation data injected at the sample input
to the link.
01: 10-bit test generation data injected at the output of the
8-bit/10-bit encoder (at the input to PHY).
10: 8-bit test generation data injected at the input of the
scrambler.
11: reserved.
Bits[3:0] in Register 0x061 determine the type of test patterns
that are injected, as follows:
0000: normal operation (test mode disabled).
0001: alternating checkerboard.
0010: 1/0 word toggle.
0011: PN sequence: long (x23 + x18 + 1).
0101: continuous/repeat user test mode; most significant
bits from 16-bit user pattern (1, 2, 3, 4) are placed on the
output for one clock cycle and then repeated. (Output user
pattern: 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, ….)
0110: single user test mode; most significant bits from the
16-bit user pattern (1, 2, 3, 4) placed on the output for one
clock cycle and then outputs all zeros. (Output user
pattern: 1, 2, 3, 4, then output all zeros.)
0111: Ramp output (dependent on test injection point and
number of bits, N).
1000: modified RPAT test sequence.
1001: unused.
1010: JSPAT test sequence.
1011: JTSPAT test sequence.
1100 to 1111: unused.
JESD204B APPLICATION LAYERS
The AD9625 supports the following application layer modes via
Register 0x063[3:0]:
0100: fS × x mode which supports line rates at integer
multiples of the sample rates
1000: single DDC mode, high bandwidth mode (only
DDC 0 used)
1001: single DDC mode, low bandwidth mode (only
DDC 0 used)
1010 to 1011: unused
1100: dual DDC mode, high bandwidth mode (both
DDC 0 and DDC 1 used)
1101: dual DDC mode, low bandwidth mode (both DDC 0
and DDC 1 used)
1110: dual DDC mode, mixed bandwidth mode (DDC 0
high bandwidth mode, DDC 1 low bandwidth mode,
samples repeated)


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