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AD9625BBP-2.5 Datasheet(PDF) 51 Page - Analog Devices |
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AD9625BBP-2.5 Datasheet(HTML) 51 Page - Analog Devices |
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51 / 74 page  Data Sheet AD9625 Rev. C | Page 49 of 72 fS × 2, fS × 4, fS × 8 Modes The JESD204B low multiplier mode application layer adds a rate conversion on top of a JESD204B transmitter/receiver with the following configuration parameters: M = 1; L = 8; S = 4; F = 1; N = 16; N' = 16; CS = 0; CF = 0; SCR = 0, 1; HD = 1; K = reference JESD204B specification. In this mode, there are five actual samples per frame and scrambling can be optionally enabled in the JESD204B interface. The transmit portion of the low multiplier mode JESD204B application layer is shown in Figure 104. The first step in this application layer is where 12-bit ADC samples are divided into six bytes. To allow the line rate of the JESD204B interface to map directly into an integer of the converter sample rate, a four to five rate conversion takes place to group the 12-bit ADC samples into blocks of five samples. During this rate conversion, for every five 12-bit ADC sample, an extra user defined, 4-bit nibble is appended to create a 64-bit frame. Next, the 64-bit low multi- plier frame maps into the four 16-bit JESD204B samples. The most significant 16-bits of the 64-bit low multiplier frame map to the oldest 16-bit JESD204B sample and the least significant 16-bits of the 64-bit low multiplier frame map to the most recent 16-bit JESD204B sample. The receive portion of the fS × 2 JESD204B application layer is shown in Figure 105. ADC SAMPLE N (12 BITS) ADC JESD SAMPLE N (16 BITS) APPLICATION LAYER DATA LINK, TRANSPORT, AND PHY LAYERS fS × 2 APPLICATION LAYER (TRANSMIT) 4/5 RATE EXCHANGE USER DEFINED (FSYNC[3:0]) ADC SAMPLE N + 1 (12 BITS) ADC SAMPLE N + 2 (12 BITS) ADC SAMPLE N + 3 (12 BITS) 48 BITS @ fS/4 64 BITS @ fS/5 64 BITS @ fS/5 ADC SAMPLE N (12 BITS) ADC SAMPLE N + 1 (12 BITS) ADC SAMPLE N + 2 (12 BITS) ADC SAMPLE N + 3 (12 BITS) ADC SAMPLE N + 4 (12 BITS) (4 BITS) S[N][11:0], S[N + 1][11:8] (16 BITS) S[N + 1][7:0], S[N + 2][11:4] (16 BITS) S[N + 2][3:0], S[N + 3][11:0] (16 BITS) S[N + 4][11:0], UD[3:0] (16 BITS) JESD SAMPLE N + 1 (16 BITS) JESD SAMPLE N + 2 (16 BITS) JESD SAMPLE N + 3 (16 BITS) JESD204B FRAMER + PHY (M = 1; L = 8; S = 4; F = 1; N = 16; N' = 16; CF = 0; SCR = 0, 1; HD = 1; K = SEE SPEC Figure 104. fS × 2 Mode Application Layer (Transmit) |
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