NT7703

6

Pad Description

Segment mode

Symbol

Function

Logic system power supply pin connects from +2.5 to +5.5V

Ground pin connects to 0V

Power supply pin for LCD driver voltage bias

" Normally, the bias voltage used is set by a resistor divider

Input pin for display data

XCK

Clock input pin for taking display data

" Data is read on the falling edge of the clock pulse

LP

Latch pulse input pin for display data

" Data is latched on the falling edge of the clock pulse

L/R

Direction selection pin for reading display data

DISPOFF

Control input pin for output deselect level

" The input signal is level-shifted from the logic voltage level to the LCD driver voltage level, and controls the

LCD driver circuit

" When DISPOFF is set to “L”, the contents of the line latch are reset, but the display data in the data latch

are read regardless of the condition of DISPOFF . When the DISPOFF function is canceled, the driver

of the LP

At that time, if the DISPOFF removal time can not keep in regulation with what is shown on the AC

characteristics, then it can not output the reading data correctly

FR

AC signal input for LCD driving waveform

" The input signal is level-shifted from the logic voltage level to the driver voltage level, and controls LCD

driver circuit

" It normally inputs a frame inversion signal

The LCD driver output pin’s output voltage level can be set to the line latch output signal and the FR signal

MD

Mode selection pin