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NLSF3T12 Datasheet(PDF) 1 Page - ON Semiconductor

Part No. NLSF3T12
Description  Quad Bus Buffer
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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NLSF3T12 Datasheet(HTML) 1 Page - ON Semiconductor

   
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© Semiconductor Components Industries, LLC, 2004
March, 2004 − Rev. 2
1
Publication Order Number:
NLSF3T125/D
NLSF3T125
Quad Bus Buffer
with 3−State Control Inputs
The NLSF3T125 is a high speed CMOS quad bus buffer fabricated
with silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
The NLSF3T125 requires the 3−state control input (OE) to be set
High to place the output into the high impedance state.
The T125 inputs are compatible with TTL levels. This device can be
used as a level converter for interfacing 3.3 V to 5.0 V, because it has
full 5.0 V CMOS level output swings.
The NLSF3T125 input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when VCC = 0 V. These
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
High Speed: t
PD = 3.8 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: I
CC = 4.0
mA (Max) at TA = 25°C
TTL−Compatible Inputs: V
IL = 0.8 V; VIH = 2.0 V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: V
OLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: Human Body Model; > 2000 V,
Machine Model; > 200 V
Chip Complexity: 72 FETs or 18 Equivalent Gates
Figure 1. Logic Diagram
Active−Low Output Enables
Y1
Y2
Y4
1
5
7
10
13
12
8
9
4
3
15
16
A1
OE1
A2
OE2
A3
OE3
A4
OE4
Y3
FUNCTION TABLE
NLSF3T125
Inputs
Output
AOE
Y
HL
H
LL
L
XH
Z
Device
Package
Shipping†
ORDERING INFORMATION
NLSF3T125MNR2
QFN−16
3000 Units/
Tape & Reel
http://onsemi.com
16
XXX
ALYW
1
MARKING
DIAGRAM
A
= Assembly Location
WL = Wafer Lot
Y
= Year
WW = Work Week
QFN−16
CASE 485G
.
(Top View)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.


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